The Cadence® JTAG Verification IP provides support for the JTAG protocol specification. It provides a mature, highly capable compliance verification solution that supports simulation, protocol checking, coverage collection, and analysis, making it applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification. JTAG VIP is compatible with the industry-standard Universal Verification Methodology (UVM) and runs on all leading simulators.
JTAG standard defines test logic that can be included in an integrated circuit to provide standardized approaches to:
The test logic consists of a boundary-scan register and other building blocks and is accessed through a Test Access Port (TAP).
Supported Specification: JTAG Specification IEEE Std 1149.1-2013.
