PMBus Verification IP

Overview

PMBus Verification IP provides an smart way to verify the PMBus component of a SOC or a ASIC. The SmartDV's PMBus Verification IP is fully compliant with standard PMBus 1.3.1 Specification and provides the following features.

PMBus Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

PMBus Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

Supports PMBus specification Revision 1.3.1.
Full PMBus Master and Slave functionality.
Supports all the PMBus commands as per the specs.
Operates as a Master, Slave, or both.
Supports all the extended and normal command codes.
- Send byte command
- Receive byte command
- Write byte command
- Write word command
- Read byte command
- Read word command
- Process call command
- Block write command
- Block read command
- Block write and read process call command
- Extended command write
- Extended command read
- Group command
- Zone write command
- Zone read command
Supports programmable clock frequency of operation.
Support Timeout detection and generation.
Alert generation and handling.
Bus-accurate timing.
Packet Error Checking(PEC) support.
Supports Master/Slave arbitration and clock synchronization.
Glitch insertion and detection.
Callbacks in Master, Slave and monitor for user processing of data.
Supports Fault Management and Reporting feature.
Supports re-synchronization of Slave.
Supports insertion of errors
- Master abort in middle of transaction
- Master doing ACK on last read access
- Master continue on NACK after write NACK from Slave
- Random and periodic clock period stretching by Slave
- Random write NACK insertion error by Slave
- Packet error check(PEC) error
- NACK for PEC code by Slave
- ACK for PEC code by Master
- Master asserted stop condition before PEC byte
- NACK for Command code byte by Slave
- NACK for second address byte after repeated start to same Slaves
- NACK for write size byte
- NACK for read size byte
- More than expected bytes were sent or received
- Less than expected bytes were sent or received
- Number of bytes field and actual bytes don't match
- NACK for read data from Master for bytes which is not last byte
- Master is driving SCL after sending NACK for read data
- Glitch insertion
- Timeout error insertion
Implements all the registers and commands as per the PMBus specification.
Monitor, Detects and notifies the testbench of all protocol and timing errors.
Compares read data with expected results.
Various kind of Master and Slave errors generation.
Status counters for various events in bus.
Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
PMBus Verification IP comes with complete testsuite to test every feature of PMBus specification.

Benefits

Faster testbench development and more complete verification of PMBus designs.
Simplifies results analysis.
Runs in every major simulation environment.

Block Diagram

Deliverables

Complete regression suite containing all the PMBus testcases.
Examples showing how to connect various components, and usage of BFM and Monitor.
Detailed documentation of all class, task and function's used in verification env.
Documentation also contains User's Guide and Release notes.

Technical Specifications

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