IP Catalog > Interface IP > Interconnect IP > PCI IP > PCI Express IP > PCI Express Controller IP > FPGA Proven PCIe Gen6 Controller IP

FPGA Proven PCIe Gen6 Controller IP

Overview

Deployed in Tier 1 Leaders. FIRST in the industry to deliver PCIe IPs across multiple generations.

  • Optimized for existing and emerging FPGA uses cases for hardening onto ASIC / SoC.
  • Best for large memory, compute-intensive and high data rate applications.

Porting support available. Previous generation IPs are available too.

Key Features

  • Supports up to x16 link width
  • Support for Tx/Rx cut-through
  • Supports 32 GT/s and 64 GT/s precoding
  • Supports 14-bit tags for TLPs (Transaction Layer Packets)
  • Supports buffering and credit management

Benefits

  • Delivers data speed up to 64GT/s (Gigatransfers per second) per lane.
  • Multi-channel packet processing and enhanced RAS capabilities ensure data integrity and simplify system integration.
  • Configurable for both Root Port and Endpoint use, it supports a wide range of applications such as high-performance computing, data centers, AI/ML, high-speed networking, to name a few.

Block Diagram

FPGA Proven PCIe Gen6 Controller IP Block Diagram

Technical Specifications

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