The MIPI DSI with C-PHY Verification IP provides an effective and efficient way to verify the components interfacing with MIPI DSI with C-PHY interface of an IP and SOC. The MIPI DSI with C-PHY VIP is fully compliant to MIPI DSI Specification version 2.2 along with MIPI C-PHY Specification version 2.1. The VIP is light weight with easy plug-and- play interface so that there is no hit on the design cycle time.
MIPI DSI v2.2 Verification IP
Overview
Key Features
- Compliant to MIPI DSI Specification version 2.2 and MIPI C-PHY Specification version 2.1 with PPI interface.
- Support all Calibration Format & operations
- C-PHY supports MFAA and SFAA for DSI TX and RX respectively for Data Lane Module in command mode.
- C-PHY supports MFAN and SFAN for DSI TX and RX respectively for data Lane Module in video mode.
- Configurable number of Data Lanes and Sub Links.
- Supports Data Lane distribution and merging in case of multilane configuration.
- Supports High-Speed, Low Power Escape, Control modes.
- Supports 16:7 Mapper and 7:16 Demapper.
- Supports symbol encoding and decoding.
- Supports dynamically configurable modes.
- Supports all Short and Long packet formats.
- Supports ECC & CRC generation as well as correction/detection.
- Supports End of Transmission packet along with EOT Sequence.
- Strong Protocol Monitor with real time exhaustive programmable checks available for each LLP, LM and PHY layer.
- Supports Dynamic as well as Static Error Injection scenarios at both Protocol and PHY layer.
- On the fly protocol checking using protocol check functions, static and dynamic assertion.
- Built in Coverage analysis.
- Provides a comprehensive user API (callbacks) in Transmitter and Receiver.
- Graphical analyser for all Layers to show transactions for easy debugging.
Benefits
- Available in native SystemVerilog (UVM/OVM/VMM) and Verilog.
- Unique development methodology to ensure highest levels of quality.
- Availability of Conformance and Regression Test Suites.
- 24X5 customer support.
- Unique and customizable licensing models.
- Exhaustive set of assertions and cover points with connectivity examples for all the components.
- Consistency of interface, installation, operation and documentation across all our VIPs.
- Provide complete solution and easy integration in IP and SoC environment.
Block Diagram
Deliverables
- MIPI DSI TX/RX BFM/Agent
- MIPI DSI Monitor and Scoreboard
- Testbench Configurations
- Test Environment & Test Suite:
- Basic and Directed Protocol Tests
- Random Tests
- Error Scenario Tests
- Assertions & Coverage Tests
- Integration Guide, User Manual and Release Notes