MIPI D-PHY Universal IP in TSMC 22ULP

Overview

The MXL-DPHY-UNIV is a high-frequency low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification for D-PHY v2.1, which is backward compatible with MIPI Specification for D-PHY v1.1. The PHY can be configured as a MIPI Master or MIPI Slave supporting camera interface CSI-2 and display interface DSI applications. The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed data traffic while low power functions are mostly used for control.

Key Features

Consists of 1 Clock lane and up to 4 Data lanes.
Supports MIPI® Alliance Specification for D-PHY Version 2.1.
Supports both high speed and low-power modes.
80 Mbps to 1.5 Gbps data rate per lane without Deskew calibration.
Up to 2.5 Gbps data rate per lane with Deskew calibration.
10 Mbps data rate in low-power mode.
Low power dissipation.
Loopback testability support.
Optional resistance termination calibrator.
Deskew calibration support.

Benefits

Supports both MIPI CSI-2 and MIPI DSI, as a transmitter and receiver
Silicon proven in TSMC 22ULP

Block Diagram

Applications

Mobile
Displays
Cameras/Sensors
IoT
VR/AR/MR
Consumer electronics
Automotive

Deliverables

Specifications
GDSII
LVS netlist
LEF file
IBIS Model
Verilog Model
Timing Model
Integration Guidelines
RTL
Documentation
One year support

Technical Specifications

Foundry, Node

TSMC, 22nm ULP

Maturity

Silicon Proven

Availability

Now

TSMC

Pre-Silicon: 22nm

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