IP Catalog > Interface IP > Memory Interface IP > DDR IP > DDR5 IP > DDR5 PHY IP > MCR DDR5 PHY

MCR DDR5 PHY

Overview

The INNOSILICON DDR Mixed-Signal MCR DDR5 PHY provides turnkey physical interface solutions for ICs requiring access to JEDEC compatible MCR DDR5 DIMM devices. It is optimized for low power and high speed applications with robust timing and small silicon area. It supports all JEDEC MCR DIMM components in the market. The PHY components contain DDR specialized functional and utility high performance I/Os, critical timing synchronization module (TSM) and a low power/jitter DLLs with programmable fine-grain control for DDR5 MCR DIMM interface.
Note that all INNOSILICON PHY is pre-assembled with.lib, LEF and GDS so that it is very easy to integrate the PHY with any existing SoC floor plan. Bus width of the MCR DDR5 PHY can be from 4 bit to 80 bit. INNOSILICON is happy to pre-assemble the PHY for our customer so that integration becomes extremely easy.

Key Features

  • Support MCR DDR5 DIMMs, standard DDR5 DIMMs and standard DDR5 signaling, rates from 20Mbps up to 9600Mbps (MCR DDR5)
  • x16/x32/x64/x72/x80 data path interface extendable, support both MCR and standard DDR5 DIMMs, or standard DDR5 SDRAM devices.
  • 1.1V JEDEC IO standard, supporting 1.1V POD_11 I/Os
  • Support DDR5 dual channel mode, dual 32bit data +8bit ECC
  • Support CA training, CS training, and write leveling training modes
  • Support Write FFE and Read DFE equalization
  • Independent read and write timing adjustments with auto calibration, dynamic V&T tracking
  • Both Read and Write Per bit deskew support
  • Support over 10 training modes for stability working
  • Support Maximum 4 frequency points fast change
  • Supports point to point memory sub systems and multi-rank
  • PVT compensation and timing calibration for all corner reliability
  • At speed BIST, scan insertion
  • Various power-down modes for low power including self-refresh support
  • APB Port register access interface
  • Implemented using 0.75V SVT/LVT/ULVT core devices and 1.2V gateoxide IO devices

Benefits

  • Fully pre-assembled design, Drop-in hard macro to ease integration and speed time to market
  • Zero risk with robust ESD architecture
  • Maintains self-refresh I/O drive state during VDD power down
  • Extensive EDA tool support for various design automation flows
  • DFI5.0 compliant memory controller interface
  • Takes full advantage of process power savings and speed capability
  • Best in class low noise design to ensure best timing margin and signal integrity
  • DFT functions to reduce test time and ensure high test coverage
  • Several programmable PHY operating modes through simple register interface
  • Per Bit De-skew to improve composite data eye during read cycles at high speed

Deliverables

  • Verilog models
  • LEF
  • Place-and-route abstracts
  • GDSII files
  • LVS netlists
  • Optional extracted HSPICE netlist for I/Os
  • Data book, Application notes
  • Silicon validation and ESD testing results
  • Optional PCB reference design and Package Electrical Model
  • Documentation

Technical Specifications

Foundry, Node
TSMC 3nm
TSMC
In Production: 3nm
Silicon Proven: 3nm
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