Innosilicon HBM2E/2 Combo PHY provides turnkey physical interface solutions for ICs requiring access to JEDEC compatible HBM devices. It is optimized for low power and high speed (up to 3.6Gbps for HBM2E, up to 2.8Gbps for HBM2) applications with robust timing and small silicon area. It supports all JEDEC HBM2E/2 SDRAM components in the market. The PHY components contain HBM specialized functional I/Os from 20Mbps up to 3.6Gbps, critical timing synchronization module (TSM) and a low power/jitter DLLs with programmable fine-grain control for any SDRAM interface.
Note that all INNOSILICON PHY is pre-assembled with.lib, LEF and GDS so that it is very easy to integrate the PHY with any existing SoC floor plan. INNOSILICON is happy to pre-assemble each PHY for our customer so that integration becomes extremely easy.
The combo PHY solution includes HBM controller and PHY, supporting HBM2E/2. With configurable timing and driving strength parameters to interface to the wide variety of SDRAMs, the PHY is very flexible with advanced command capability to increase SDRAM operation efficiency.
HBM2E/2 Combo PHY&Controller
Overview
Key Features
- HBM2E/2 modes & signaling, rates from 20Mbps up to 2800Mbps (HBM2) and 3600Mbps (HBM2E) respectively
- Support up to 8 Channel with 128 DQ width + Optional ECC pin support/channel
- 1.2V JEDEC IO standard, support programmable 18mA driver with calibration
- Self-Refresh feature included
- Independent read and write timing adjustments with auto calibration
- Multiple receivers for power and speed trade off
- Balanced clock tree to reduce skew among bits
- Low jitter with superior noise rejection
- Various clock gating and low power modes
- Write WDQS and Read RDQS strobe separately
- Support write mask/ECC/command and address parity
- Measures taken to reduce simultaneous switching power/noise, for both DBI on and off
- PVT compensation and timing calibration for all corner reliability
- At speed BIST, scan insertion, PAD and internal loopback modes
- APB Port register access interface
- Self-heating and aging effect carefully evaluated,IR/EM fixed to the best possible
- Support micro-bump and TSV package
- Interposer routing straight across Controller and DRAM with unified routing length for all bits
- Interoperability Testing Supports any third-party DFI 4.0-compliant memory controller vendor
- Support IEEE1500 port for direct access to the memory stack and PHY
Benefits
- Fully pre-assemble design, Drop-in hard macro to ease integration and speed time to market
- Maintains self-refresh I/O drive state during VDD power down
- Extensive EDA tool support for various design automation flows
- Optional CKE retention mode permits VDD and all non-essential I/Os to be powered down while retaining the external SDRAMs in self refresh mode
- DFI4.0/5.0 compliant memory controller interface
- Integration with other INNOSILICON interface IP
- Takes full advantage of process power savings and speed capability
- Best in class low noise design to ensure best timing margin and signal integrity
- DFT functions to reduce test time and ensure high test coverage
- Several programmable PHY operating modes through simple register interface
- Per Bit De-skew to improve composite data eye during read cycles at high speed
Applications
- High performance computing
- Artificial intelligence
- GPU
Deliverables
- Verilog models
- LEF
- Place-and-route abstracts
- GDSII files
- LVS netlists
- Optional extracted HSPICE netlist for I/Os
- Data book, Application notes
- Silicon validation and ESD testing results
- Optional PCB reference design and Package Electrical Model
- Documentation: Documentation for the Innosilicon PHY will be delivered as part of the access package.
Technical Specifications
Foundry, Node
TSMC 14/12/7nm,Samsung14nm, SMIC14nm,GF14/12nm
Maturity
SP or DR
SMIC
In Production:
14nm
Silicon Proven: 14nm
Silicon Proven: 14nm
TSMC
In Production:
12nm
,
16nm
Silicon Proven: 12nm , 16nm
Silicon Proven: 12nm , 16nm