The Innosilicon 12.5G SERDES PHY is a highly configurable PHY capable of supporting speeds up to 12.5Gbps within a single lane. For this particular datasheet, the PHY has been configured to support HMC-12.5G-VSR specifically, but the PHY itself can be configured to support a wide range of HS SERDES protocols through changes to the PCS layer and register settings.
The PHY is physically configured in order to support multi-lane solutions. There is a common block with Tx PLL, reference clock input, bandgap, bias circuitry and termination calibration. This common block can then support up to 4 lanes of Tx/Rx.
12.5G Multi-SerDes PHY
Overview
Key Features
- Reference Clock:
- 25-300MHz, integer multiple of Serial output
- +/-300ppm frequency stability (<8Gbps)
- +/-100ppm frequency stability (>=8Gbps)
- Support both SRNS & SRIS modes
- Configurable as reference clock repeater
- Internal PLL:
- Used to drive all PHY transmitters and receivers
- LC-tank architecture operational from 16-32 Gbps
- Ring PLL covering 1.0-6Gbps
- Programmable pre-divider & feedback divider
- Initiative SSC or reference clock based passive SSC
- LOCK indication
- Data Transmit:
- Rates supported from 1.0-32 Gbps
- AC coupled
- 50? impedance, internally calibrated
- 3 tap pre/post-cursor de-emphasis, programmable
- 200-1000mV differential peak-peak, programmable
- Programmable Rise/Fall times
- Data Receive:
- AC coupled
- 50? impedance, internally calibrated
- 200-1200mV differential peak-peak
- CTLE, programmable
- DFE, 6-tap programmable
- CDR
- Testing:
- Scan
- BIST with PRBS7, PRBS23 and PRBS31 (PG & SD)
- Loopback
- On-chip scope
- Analog and digital probe points
- HTOL
- IDDQ
- ESD:
- HBM 2000V, [JEDEC JS-001-2014]
- MM100V, [JEDEC JESD22-A115C]
- CDM 250V, [JEDEC JESD22-C101F]
- Latch Up: +-200mA for IO and 1.5*Vsupply for power rails
- Package:
- Wire bond with careful SI/PI analysis for 8Gbps and below
- Flip-Chip with careful SI/PI analysis for 8Gbps and Up
- Interface with controller:
- PIPE4.3 & 32 bits data bus for PCIe and USB3.x
- SAPIs for SATA3.0
- UTMI+ (level3) 8/16bit for USB2.0 (as a separated IP not described in this document)
- XGMII for XAUI/10GbE
- Serdes interface for customized PCS
Benefits
- As with all Innosilicon IP, the focus is on silicon proven, fully certified solutions providing:
- Small size
- Low power
- High ATE coverage
- Simple integration
- Flexible customization
Deliverables
- Verilog Sim Behavioral simulation model for the PHY
- Encrypted IO spice netlist for SI evaluation
- Integration Guidelines
- Test Guidelines
- GDSII Layout and layer map for foundry merge
- Place and Route LIB and LEF views for the AFE
- LVS and DRC verification reports
Technical Specifications
Foundry, Node
SMIC/TSMC/UMC 40nm
GLOBALFOUNDRIES
Pre-Silicon:
28nm
SLP
SMIC
In Production:
40nm
LL
Silicon Proven: 40nm LL
Silicon Proven: 40nm LL
TSMC
In Production:
40nm
LP
Silicon Proven: 40nm LP
Silicon Proven: 40nm LP
UMC
In Production:
40nm
Silicon Proven: 40nm
Silicon Proven: 40nm