Serdes IP
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20G MSS (Multi-standard SerDes) PHY
- Developing under SF4X CMOS technology (2025.06.30 MTO)
- Compliant to multiple standards, max datarate 20Gb/s
- Channel Configuration for Data Lanes: 1, 2 or 4 Data Lanes
- Reliable Ring OSC PLL based architecture for Low power consumption
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100G SerDes PAM4 PHY
- The SERDES PHY IP delivers a high-performance, low-power solution for high-speed interfaces up to 112Gbps.
- It supports diverse applications including AI accelerators, data centers, 5G infrastructure, and automotive SoCs.
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Automotive Grade PLLs, Oscillators, SerDes PMAs, LVDS/CML IP
- TSMC IP9000 Alliance member enabling automotive IP support in TSMC automotive processes
- Automotive Documentation including Safety Manual, FMEDA and DFMEA
- Design reliability report containing EM/IR and Aging analysis
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112G Multi-SerDes
- Designed with a small footprint, ultra-low latency, and low power consumption, the 112G SerDes maximizes bidirectional memory access efficiency, reduces software complexity, and helps chip developers leverage existing Ethernet infrastructure to significantly lower Total Cost of Ownership (TCO).
- Featuring IEEE 802.3-compliant Forward Error Correction (FEC), 35dB ultra-high channel loss compensation, and adaptive high-speed equalization technologies (CTLE, FFE), it provides full-cycle link protection—from error correction to pre-warning—enabling highly compatible, stable, and efficient chip-to-chip connectivity solutions.
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Multi-Rate Serdes IP Solution
- YouPHY-Serdes provides 2.5-32Gbps multi-rate SERDES IP which is designed for smooth integration of Multiple SERDES lanes demonstrate good performance class performance, area and power.
- The programmable PHY supports major standards such as PCIe Gen 4.0/3.0/2.0/1.0, USB 3.1/3.0, XAUI, SATA Gen 3.0/2.0/1.0, CEI-11G-LR, 10GBase-KX4, JESD204B, SGMII/QSGMII, RAPID I/O, HSSTP (Trace Port), V-By-One, DisplayPort and HMC.
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High-Speed LVDS (SERDES) Transceiver
- The LVDS_SERDES IP Core is a high-speed LVDS transmitter / receiver pair suitable for a wide range of serial interface applications.
- The design is comprised of an independent transmitter and receiver that may be used separately or together as a single transceiver.
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Combo SerDes
- 4 Channels per Quad
- Data rate up to 25/28/32Gbps
- Shared Quad LC-PLL for high performance
- Independent Ring-PLL of each channel for clock flexibility
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64G SerDes
- 4 Channels per Quad, ≤64Gbps; PAM4 support 25~64Gbps; NRZ support 2.5~32Gbps
- Serialization/Deserialization interface width; 64/32/16bits; 64-bit parallel data path in PAM4 mode; 32-bit parallel data path in full-rate NRZ mode; 16-bit and 32-bit parallel data path widths in half-rate and quarter-rate modes
- Four programmable transmitter and receiver configurations selectable by port by using hardware pins or registers. Facilitates fast speed switching during speed negotiation routines
- Aggressive equalization capability to enable 64Gbps operation and legacy system upgrades
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112G SerDes USR & XSR
- 8 Channels per Macro, 2.5Gbps~112Gbps with TX/RX independent; NRZ Data Rate:2.5-56Gbps PAM4 Data Rates: 56-112Gbps
- Serialization/Deserialization interface width; PCS-User interface support 64bit in PIPE
- Two cascaded PLLs, one LC-tank based and the other ring-oscillator based
- Digitally-control-impedance termination resistors
