Serdes IP

Compare 172 Serdes IP from 32 vendors (1 - 10)

PCIe 3.0 Serdes PHY IP, Silicon Proven in TSMC 22ULP
- Compliant with PCIe 3.0 Base Specification
- Compliant with PIPE 4.3
- Supported data transfer rate: 2.5 GT/s, 5.0 GT/s and 8.0 GT/s
- Supported physical lane width: x4
Multiprotocol SerDes PMA
- Supports over 30 protocols including CEI 6G & 11G SR, MR, LR, Ethernet 10GBASE-X/S/K/R, PCIe Gen1/2/3/4, V-by-One HS/US, CPRI, PON, OTN/OTU, 3GSDI, JESD204A/B/C, SATA1-3, XAUI, SGMII
- Programmable (De)Serialization width: 8, 10, 16, 20, 32, or 40 bit
- Tx ring PLL includes fractional multiplication, spread spectrum and Jitter Cleaner function for Sync-E and OTU
- Core-voltage line driver with programmable pre-and post-emphasis
1-112Gbps Integrated Laser Driver and Optical SerDes
- Optical Optimization:
- Integrated laser driver
- RX front-end architected for optical signaling
- Non-linear DSP equalization that corrects for both static and dynamic nonlinearity components.
1-112Gbps Medium Reach (MR) and Very Short Reach (VSR) SerDes
- High speed performance
- Low power architecture
- Sub-sampling clock multiplier
Xtra-Long-Reach (XLR) Multi-Standard-Serdes (MSS)
- Most Likely Sequence Detector(MLSD)
- High speed A/D
- Sub-sampling clock multiplier
- Master Controller
1-112Gbps Long-Reach (LR) Multi-Standard-Serdes (MSS)
- High speed A/D
- Sub-sampling clock multiplier
- Master controller
Ethernet SerDes - 16Gbps and 10Gbps multi-protocol SerDes PHY
- Wide range of protocols that support networking, HPC, and applications
- Low-latency, long-reach, and low-power modes
- Multi-Link PHY—mix protocols within the same macro
- EyeSurf —non-destructive on-chip oscilloscope
- Extensive set of isolation, test modes, and loop-backs including APB and JTAG
- Supports 16-bit, 20-bit, and 32-bit PIPE and non-PIPE interfaces
- Selectable serial pin polarity reversal for both transmit and receive paths
224G-LR SerDes PHY enables 1.6T and 800G networks
- Optimized Performance, Power and Area with Design Agility
- Supports full-duplex 1.25 to 225Gbps data rates
- Enables 1.6T, 800G, 400G, and 200G Ethernet with a PHY + Controller solution
- Supports evolving IEEE 802.3 and OIF-CEI-224G standard electrical specifications
- Meets the performance requirements of chip-to-module (VSR), chip-to-chip (MR), and copper/backplane (LR) interconnects
112G-VSR PAM4 SerDes PHY - PPA optimized for short reach connectivity
- 1.25Gbps to 116Gbps flexible data rates allowing simultaneous support of different protocols including Ethernet and OTN
- Power optimized for short-reach applications with configurability
- Superior bit error rate (BER) with extra performance margin beyond short-reach standard requirements
- Beachfront optimized floorplan allows north-south and east-west SoC edge placement
- Comprehensive on-chip diagnostic features make system testing and debugging quick and easy
- Enables 800Gbps networking with PHY and Controller solutions
Ethernet 10G KR Serdes
- Quad Channel Multi Lane Macro
- Integrated backplane PCS, PMA layer
- High-Speed Data Transfer