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12
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from 6 vendors
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10)
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1:6 Fixed Length Visually Lossless Compression/Decompression
- Partial Update
- Random access
- No rate control needed
- Easy bandwidth compression/decompression control
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1:3 Fixed Length Visually Lossless Compression/Decompression
- Partial Update
- Random access
- No rate control needed
- Easy bandwidth compression/decompression control
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1:6 Fixed Length Visually Lossless Compression/Decompression
- Partial Update
- Random access
- No rate control needed
- Easy bandwidth compression/decompression control
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1:4 Fixed Length Visually Lossless Compression/Decompression
- Partial Update
- Random access
- No rate control needed
- Easy bandwidth compression/decompression control
-
1:3 Fixed Length Visually Lossless Compression/Decompression
- Partial Update
- Random access
- No rate control needed
- Easy bandwidth compression/decompression control
-
1:2 Fixed Length Visually Lossless Compression/Decompression
- Partial Update
- Random access
- No rate control needed
- Easy bandwidth compression/decompression control
-
1:2 Fixed Length Visually Lossless Compression/Decompression
- Partial Update
- Random access
- No rate control needed
- Easy bandwidth compression/decompression control
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Sub-Nanosecond Resolution, Sub-Microsecond Accurate, FPGA System Timer Component
- Flexible and independent clocks for control-plane and reference clock
- Up to 32 outputs, each in their own clock domain
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Multiplexer - amplifier
- SMIC CMOS 0.18 um
- Input and output matching 50 Ohm
- No external matching components required
- Built-in adjustment of matching
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Single precision, IEEE 754, floating point square root
- Single-precision (32-bit) floating point square root.
- IEEE compliant.
- Full support for infinities, NaNs and denormals.
- Rounding is to the nearest even number.