The future of tooling from IP configuration to SoC verification
The modern SoC typically consists of billions of transistors and is normally designed with many modular IP blocks. Each of these blocks have been commercially licensed, developed or reused from previous designs. Integrating these components can be time-consuming and error-prone, which is continually getting more complex thanks to:
- Increased system complexity: consumers are demanding even more functionality for their connected lives
- Smaller processor technology: technology has accelerated through 10nm and below (but with higher risks and lower yields)
- Increased consumer cycles: products are now often refreshed at 6-12 months (and this is only getting faster), which is driving silicon design cycles
To read the full article, click here
Related Semiconductor IP
- 1.8V/3.3V I/O library with ODIO and 5V HPD in TSMC 16nm
- 1.8V/3.3V I/O Library with ODIO and 5V HPD in TSMC 12nm
- 1.8V to 5V GPIO, 1.8V to 5V Analog in TSMC 180nm BCD
- 1.8V/3.3V GPIO Library with HDMI, Aanlog & LVDS Cells in TSMC 22nm
- Specialed 20V Analog I/O in TSMC 55nm
Related Blogs
- From DIY To Advanced NoC Solutions: The Future Of MCU Design
- World IP Day: A Time to Reflect on the Value of Semiconductor IP
- DDR5 12.8Gbps MRDIMM IP: Powering the Future of AI, HPC, and Data Centers
- Migrating the CPU IP Development from MIPS to RISC-V Instruction Set Architecture
Latest Blogs
- Cadence Unveils the Industry’s First eUSB2V2 IP Solutions
- Half of the Compute Shipped to Top Hyperscalers in 2025 will be Arm-based
- Industry's First Verification IP for Display Port Automotive Extensions (DP AE)
- IMG DXT GPU: A Game-Changer for Gaming Smartphones
- Rivos and Canonical partner to deliver scalable RISC-V solutions in Data Centers and enable an enterprise-grade Ubuntu experience across Rivos platforms