Four questions about Moore's Law, 28nm and the future of IP design
August 5, 2014
A few weeks ago Brian Bailey, the well-known technology editor for EDA at Semiconductor Engineering, kindly asked me to provide some comments in relation to a set of very interesting questions on the fate of Moore’s Law and the adoption of sub-20nm process nodes. You can find a selection of my answers, alongside opinions and thoughts from a slew of industry experts, in his recently published comprehensive article: Moore’s Law Tail No Longer Wagging The Dog. I wouldlike to thank Brian for this opportunity and look forward to more articles from him on this topic; if you’re interested in my opinions on IP development in the context of Moore’s Law, please find my answers in full below.
To read the full article, click here
Related Blogs
- Navigating the challenges of manual IP design migrations
- DDR5 12.8Gbps MRDIMM IP: Powering the Future of AI, HPC, and Data Centers
- Moore's Law and 28nm Yield
- Moore's Law Has Stopped at 28nm!
Latest Blogs
- Cadence Announces Industry's First Verification IP for Embedded USB2v2 (eUSB2v2)
- The Industry’s First USB4 Device IP Certification Will Speed Innovation and Edge AI Enablement
- Understanding Extended Metadata in CXL 3.1: What It Means for Your Systems
- 2025 Outlook with Mahesh Tirupattur of Analog Bits
- eUSB2 Version 2 with 4.8Gbps and the Use Cases: A Comprehensive Overview