In Mixed-Signal SoC Verification, Say Good-bye to the Black Box Problem
There are some inescapable truths in electronics design: The more challenges we overcome, the more we want to confront new ones and topple them.
Today, we know, the level of complexity for most designs is staggering. To achieve our cost and form factor design goals, we are deep into the era of mixed-signal design and system integration. Complex systems-on-chip (SoC) not only have to include blocks of digital and analog circuits, but they must be verified now together, not separately.
The prior methodologies of integrating and verifying this IP--black box IP, whether digital or analog--is no more because engineers must understand the functionality of the complete system, including how each "black box" is interacting with its neighbors and the larger system.
Related Semiconductor IP
- RISC-V CPU IP
- AES GCM IP Core
- High Speed Ethernet Quad 10G to 100G PCS
- High Speed Ethernet Gen-2 Quad 100G PCS IP
- High Speed Ethernet 4/2/1-Lane 100G PCS
Related Blogs
- Real Number Model Development and Application in Mixed-Signal SoC Verification
- T&VS delivers Emulation and Validation services for Mobile SoC
- SoC verification through Managed service
- T&VS provides end-to-end DFT solution for Consumer SoC
Latest Blogs
- Why Choose Hard IP for Embedded FPGA in Aerospace and Defense Applications
- Migrating the CPU IP Development from MIPS to RISC-V Instruction Set Architecture
- Quintauris: Accelerating RISC-V Innovation for next-gen Hardware
- Say Goodbye to Limits and Hello to Freedom of Scalability in the MIPS P8700
- Why is Hard IP a Better Solution for Embedded FPGA (eFPGA) Technology?