IP Cannot be an Efficient Abstraction Level Without SystemC!
EDN recently featured a lengthy article entitled "SOCs: IP is the new abstraction. Reusable IP, not system-level language, has become the new level of abstraction."
The point of view is that SoC design now is such a large undertaking that the best way to efficiently design one is to assemble IP from various sources into a platform, differentiate with software, and swap in different IP for derivative designs that target different requirements.
It all makes sense. However, where it goes wrong is in saying that SystemC has not delivered the next level of abstraction after RTL. This IP re-use and assembly vision does not work very efficiently unless the IP is developed in SystemC transaction-level modeling (TLM). Designing blocks in RTL would work in this vision, but it would be very inefficient, blunting many of the benefits. This is why many corporate design re-use initiatives have stalled, because of the significant amount of overhead required to re-use RTL.
To read the full article, click here
Related Semiconductor IP
- Root of Trust (RoT)
- Fixed Point Doppler Channel IP core
- Multi-protocol wireless plaform integrating Bluetooth Dual Mode, IEEE 802.15.4 (for Thread, Zigbee and Matter)
- Polyphase Video Scaler
- Compact, low-power, 8bit ADC on GF 22nm FDX
Related Blogs
- Quantum Safe IP: Hardware Level Security for the Quantum Computing Era
- Tips on Using e Macros to Raise Abstraction and Facilitate Reuse
- Automation without abstraction is like a bicycle without pedals
- IP-SoC trip report (part II): system level mantra
Latest Blogs
- FiRa 3.0 Use Cases: Expanding the Future of UWB Technology
- Cadence Announces Industry's First Verification IP for Embedded USB2v2 (eUSB2v2)
- The Industry’s First USB4 Device IP Certification Will Speed Innovation and Edge AI Enablement
- Understanding Extended Metadata in CXL 3.1: What It Means for Your Systems
- 2025 Outlook with Mahesh Tirupattur of Analog Bits