Beware the IP mismatch in FPGA debug
January 26, 2010
Incorporating 3rd party IP in a complex ASIC design is a fairly standard practice these days. There's a lot of great functionality available, it saves time compared to designing from scratch, and by and large the IP is of good quality if you get it from a reputable supplier.
Should work the same for FPGAs right? Sounds simple enough - plug in the IP you need and verify it with the context of your entire design. You've got enough simulation horsepower and you can synthesize right to your FPGA target.
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Related Semiconductor IP
- Temperature Glitch Detector
- Clock Attack Monitor
- SoC Security Platform / Hardware Root of Trust
- SPI to AHB-Lite Bridge
- Octal SPI Master/Slave Controller
Related Blogs
- FPGA Debug Is Harder Than You Think
- What are you ready to mobilize for FPGA debug?
- Why is Hard IP a Better Solution for Embedded FPGA (eFPGA) Technology?
- Why Choose Hard IP for Embedded FPGA in Aerospace and Defense Applications