The formal verification market is still untapped
October 20, 2009
Functional verification is a major bottleneck in the chip design cycle Any misstep in closing the functional correctness of a digital system costs millions of dollars in redesign, additional testing, and silicon respins. One can argue at length about its actual cost, but people in the industry usually agree that functional verification takes between 40 and 70% of a project’s labor, and about 50% of the total cost.
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