Heard at DAC: another try at embedded FPGA IP for SoCs

By _EDN Practical Chip Design

June 17, 2010

The concept of integrating an FPGA into a platform SoC has immediate appeal. Most of the functions in an SoC-CPUs, memories, standard accelerators, even many interfaces-stay exactly the same across a wide range of customer requirements in a given application area. Only a few hardware requirements, such as an accelerator for a proprietary algorithm, perhaps, or a clever DMA engine or unique I/O controller, must change from customer to customer. It would be great to have a moderate-sized FPGA on the die that could implement such variations without mask spins, and without the chip crossings and added package count of an external FPGA.

In fact this idea was quite fashionable several years ago. But it went hard aground on a number of difficult shoals. FPGA fabric design is difficult. Even after you decide on a logic cell and interconnect architecture, the electrical design is challenging. A good blend of density, power, and speed is elusive. And the passgates used in the interconnect want special process tweaks, or interconnect speed becomes an issue. These considerations led most attempts at embedded FPGA fabric to be custom designs delivered as hard IP. But hard IP has to be redesigned for every process variant. And since the block you have is never exactly the block any customer wants, you end up redesigning for every design win as well.

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