Ideas from ISQED: how Denali beats verification bloat

By _EDN Practical Chip Design

March 24, 2010

The International Symposium on Quality Electronic Design is one of those almost quirky small conferences so rich in surprises that it always seems to be worth the time. The organizers clearly interpret the conference theme freely, so topics range from verification to fault- or variation-tolerant design to conceptual subjects like defining architectural quality.

One of this morning's keynotes was of particular interest to SoC design teams. Denali CTO and CFO—surely one of the most interesting titles in the industry—Mark Gogolewski spoke on dealing with the cost of verification. Gogolewski opened with a powerful generalization: "The cost of quality is creating havoc in the industry." He went on to document his claim, and to offer by way of solution a recent design experience at Denali. Remarkably for keynotes, Gogolewski's solution didn't involve licensing anything from Denali.

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