Altera at 28nm: rethinking the FPGA
February 2, 2010
Altera this morning took the unusual step of discussing their architectural strategy for the next generation of FPGAs far in advance of even product sampling. The reasons is that for Altera at least, 28nm will mark a clear inflection point between the days when FPGA roadmaps were driven by Moore's-Law scaling and the era in which it will require major architectural innovations to deliver better performance in customers' applications.
To read the full article, click here
Related Semiconductor IP
- SLVS Transceiver in TSMC 28nm
- 0.9V/2.5V I/O Library in TSMC 55nm
- 1.8V/3.3V Multi-Voltage GPIO in TSMC 28nm
- 1.8V/3.3V I/O Library with 5V ODIO & Analog in TSMC 16nm
- ESD Solutions for Multi-Gigabit SerDes in TSMC 28nm
Related Blogs
- Altera and Xilinx Eyeing 28nm FPGA Dominance
- Altera's intros 28nm Stratix V FPGA family
- Xilinx unleashes triad of low-power, 28nm FPGA families with very promising characteristics for memory interfacing
- TPACK's role in Altera designs
Latest Blogs
- Half of the Compute Shipped to Top Hyperscalers in 2025 will be Arm-based
- Industry's First Verification IP for Display Port Automotive Extensions (DP AE)
- IMG DXT GPU: A Game-Changer for Gaming Smartphones
- Rivos and Canonical partner to deliver scalable RISC-V solutions in Data Centers and enable an enterprise-grade Ubuntu experience across Rivos platforms
- ReRAM-Powered Edge AI: A Game-Changer for Energy Efficiency, Cost, and Security