USB 3.0 PHY IP for UMC
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USB 3.0 PHY IP
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15
USB 3.0 PHY IP
for UMC
from 6 vendors
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10)
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USB3.0 build-in clock PHY, UMC 40LP, type-C
- Smallest USB 3.2 Gen1x1 BCK PHY IP worldwide (e.g. IP size @40nm <0.36mm²)
- Fully compliant with Universal Serial Bus USB 3.2 Gen1x1, 2.0, and 1.1 electrical specifications
- Supports clock outputs from the internal BCK module
- Real-time calibrations to ensure frequency accuracy
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USB 3.0 PHY in UMC (65nm, 40nm)
- Complete mixed-signal physical layer for USB 3.0 applications
- Includes all circuitry needed for operation at all USB speeds (SuperSpeed, High-Speed, FullSpeed, Low-Speed)
- USB-C 3.0 femtoPHY supports Type-C reversible connectors
- Optimized PHY area (<0.5mm2 for USB 3.0, <0.8mm2 for USB-C 3.0)
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USB 3.0 femtoPHY in UMC (28nm, 12nm)
- Complete mixed-signal physical layer for USB 3.0 applications
- Includes all circuitry needed for operation at all USB speeds (SuperSpeed, High-Speed, FullSpeed, Low-Speed)
- USB-C 3.0 femtoPHY supports Type-C reversible connectors
- Optimized PHY area (<0.5mm2 for USB 3.0, <0.8mm2 for USB-C 3.0)
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PCIe 3.0/3.1/USB3.0/SATA3 Combo PHY
- Standard PHY interface enables multiple IP sources for PCI Express Logical Layer and provides a target interface for PCI Express PHY vendors.
- Supports 2.5Gb/s only or 2.5Gb/s,5.0Gb/s and 8.0Gb/s serial data transmission rate
- Utilizes 8-bit, 16-bit or 32- bit parallel interface to transmit and receive PCI Express data
- Allows integration of high speed components into a single functional block as seen by the endpoint device designer.
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USB 3.0 PHY
- 5-Gbps SuperSpeed data transmission rate through 3-m USB 3.0 cable
- Spread Spectrum clock (SSC) generation and absorption
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USB 3.0 PHY
- 5.0 Gbps
- Complies with USB 3.0 Specification