Overcoming Latency in PCIe Systems

Overcoming PCI Express (PCIe) latency isn't simply a matter of choosing the lowest-latency components from among those suitable for an embedded-system design, but it's a good place to start.

It's also a matter of architecting operations to reduce or eliminate the sensitivity of system performance to latency. It's impossible to mask all the latency, so the less there is to begin with, the better.

Defining Latency

Latency is the delay between starting and completing an action. For a switch, it's the time between the start-of-packet (SoP) symbol on an input pin and the SoP symbol on an output pin for the same packet forwarded through the switch.

From an endpoint's perspective, the latency includes the packet transmission time, since it can't use the data until it has seen the cyclic redundancy check (CRC) at the end and checked for errors. At the highest level, the overall task latency, which may include multiple switch latencies, is what really matters. At issue is whether resources are idled during the waiting period implied by a task or transfer latency, and whether the waiting time prevents a deadline from being met.

A PCIe switch's latency can be decomposed into the time required to receive the header, a pipeline delay and a queuing delay. The pipeline delay is the length of time for a packet to traverse an otherwise empty switch and is solely a function of the switch's design.

The queuing delay depends to a large extent upon the traffic pattern but can also be dependent on flow control credits, as well as the switch's arbitration and scheduling policies. Deficiencies in a switch's implementation or architecture most often show up when dealing with flows consisting primarily of short packets.

Therefore, a switch's performance should be evaluated with short packets, long packets, and, of course, with a packet mix and flow pattern representative of the application.

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