10 Gbps Ethernet IP
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IP
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10 Gigabit Ethernet PCS/PMA with FEC/Auto-Negotiation (10GBASE-KR)
- Designed to 10-Gigabit Ethernet specification IEEE 802.3-2012 clause 49, Forward Error Correction (FEC) clause 74, and Auto-Negotiation clause 73
- Optional Management Data Interface (MDIO) interface to manage PCS/PMA registers according to specification IEEE 802.3-2012 clause 45
- Available under the Xilinx Project Core License Agreement
- Supports LAN mode only
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10 Gigabit Ethernet PCS/PMA (10GBASE-R)
- Designed to 10-Gigabit Ethernet specification IEEE 802.3-2012 clause 49
- 1588 hardware timestamping support available through AXI 10G Ethernet IP
- Optional Management Data Interface (MDIO) interface to manage PCS/PMA registers according to specification IEEE 802.3-2012 clause 45
- Supports LAN mode only
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10 Gigabit Ethernet XGMAC IP
- Full-duplex mode at 10 Gbps
- Supports XGMII interface
- Independent 64-bit scatter-gather DMA with big/little endian operation
- PAUSE frame based flow control in full-duplex mode
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10 Gigabit Ethernet Media Access Controller (10GEMAC)
- Designed to IEEE 802.3-2012 specification
- 1588 hardware timestamping support available through AXI 10G Ethernet IP
- Optional 32-bit low latency 10G Ethernet MAC or 64-bit Ethernet MAC supporting 10G data rates
- Choice of external XGMII or internal FPGA interface to PHY layer
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10G Ethernet TSN Subsystem
- 10G Ethernet MAC/PCS with 802.1CM (802.3br/802.1bu) preemption and interspersed express traffic feature for MAC+PCS/PMA
- Designed to the 25G Ethernet requirements for 10/25 Gb/s operation specified by IEEE 802.3 Clause 49, IEEE 802.3by, and the 25G Ethernet Consortium
- Low latency 64-bit 10G Ethernet MAC and BASE-R IP
- Allows multiple instantiations up to by 4
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TSN Ethernet Endpoint Controller
- The TSN-EP implements a configurable controller meant to ease the implementation of endpoints for networks complying to the Time Sensitive Networking (TSN) standards.
- It integrates hardware stacks for timing synchronization (IEEE 802.1AS-2020) and traffic shaping (IEEE 802.1Qav and 802.1Qbv), frame-preemption (IEEE 802.1Qbu and IEEE 802.3br) and a low-latency Ethernet MAC.
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UltraScale+ Integrated 100G Ethernet Subsystem
- Optional built-in 100G RS-FEC
- Supports 10 lanes x10.3125 CAUI-10, 4 lanes x25.78125G CAUI-4 or dynamically switchable CAUI-4 and CAUI-10 mode
- Requires license key available at no charge
- 1588 1-step and 2-step hardware time stamping