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Gen-Z Switch IP Core
- Full Verilog/SystemVerilog core
- Compliant with the Gen-Z 1.1 Core Specification
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Gen-Z Link Layer IP Core
- Full Verilog/SystemVerilog core
- Compliant with the Gen-Z 1.0 Core Specification
- Explicit Link Local Flow Control credit management
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Gen-Z Physical Layer for PCIe IP Core
- Full Verilog/SystemVerilog core
- Compliant with the Gen-Z 1.1 Physical Layer Specification
- Compliant with the Gen-Z 1.1 Physical Layer Abstraction interface
- Multi-lane symmetric link support up to 16 lanes per link
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Gen-Z Physical Layer for 802.3 IP Core
- Full Verilog/SystemVerilog core
- Compliant with the Gen-Z 0.5d Physical Layer Specification
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Gen-Z Requester IP Core
- Full Verilog/SystemVerilog core
- Compliant with the Gen-Z 1.1 Core Specification
- Explicit OpClass support (Core64, Control and Atomic, etc.)
- Non-idempotent Atomic operation handshake support (NIRR/NIRR Ack)
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Gen-Z Responder IP Core
- Full Verilog/SystemVerilog core
- Compliant with the Gen-Z 1.0 Core Specification
- Explicit Op-Class support (Core64, Control, Atomic, etc.)