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Compare 15 Other from 4 vendors (1 - 10)
  • Simulation VIP for SMBus
    • SMBus Devices
    • Controller target, or host
    • Packet Error Checking
    • Performs PEC on transmit and receive data on applicable packets
    Block Diagram -- Simulation VIP for SMBus
  • IPSec Verification IP
    • Provides Ethernet fully compliant to 802.3-2018 supporting all media independent interfaces for (1/10/25/40/50/100/200/400/800 G)
    • Provides IPSec as per RFC-4301 specification
      • Supports Tunnel Mode and Transport Mode
      • Supports Authentication header (AH)
      • Supports Encapsulating Security Payload (ESP)
      • Supports Manual as well as automatic Key Exchange
      • Encodes and decodes Ip headers
      • Protects and validates ipSec using AES-GCM Cipher suites
      • Cryptographic protection
    • Supports Tunnel Mode and Transport Mode
    • Supports Authentication header (AH)
    Block Diagram -- IPSec Verification IP
  • UART/USART Verification IP
    • Available in UVM, System UVM, UVM.
    • According to the National Semiconductor PC16550D Compliance.
    • Supports Simplex and Duplex mode.
    • Independently controlled transmit, receive, line status, and data set interrupts
    Block Diagram -- UART/USART Verification IP
  • SPI/QSPI/OSPI Verification IP
    • SPIAvailable in UVM, System UVM, UVM.
    • Error response types supported.
    • Multi-Slave and Single-Master support.
    • Rich set of configuration parameters for each individual Slave Agent
    Block Diagram -- SPI/QSPI/OSPI Verification IP
  • SMBus Verification IP
    • Fully compliant with Rev. 3.1 of the SMBus Specification
    • Support PEC (Packet error Checking) for communication robustness.
    • Support for all Bus protocols with and without PEC.
    • Support for SMBus ARP (Address Resolution Protocol) for dynamically assigning a unique address to each slave device.
    Block Diagram -- SMBus Verification IP
  • RTC Verification IP
    • Compliant to RTC basic specification as defined in DS3234 maxim_spi_rtc
    • Supports configurable timing parameters and multi-slave configurations.
    • Supports multi-slave memory.
    • Supports Master and Slave Mode.
    Block Diagram -- RTC Verification IP
  • PMBus Verification IP
    • Fully compliant with Rev. 1.4 of the PMBus Specification.
    • Support for all SMBus protocols with and without PEC (Packet Error Checking).
    • Support for SMBus ARP (Address Resolution Protocol) for dynamically assigning a unique address to each slave device.
    • Support Group command protocol for multiple PMBus device communication.
    Block Diagram -- PMBus Verification IP
  • ARINC 429 IP Core
    • Implements ARINC 429 Data Bus Communication Protocol.
    • Supports both Transmit and Receive functionality for ARINC 429 words.
    • Configurable data rates for flexible integration into avionics systems.
    • Provides advanced error detection mechanisms for high data integrity.
    • Bare-metal application or PetaLinux OS with associated APIs.
    Block Diagram -- ARINC 429 IP Core
  • Gen-Z Switch IP Core
    • Full Verilog/SystemVerilog core
    • Compliant with the Gen-Z 1.1 Core Specification
  • Gen-Z Link Layer IP Core
    • Full Verilog/SystemVerilog core
    • Compliant with the Gen-Z 1.0 Core Specification
    • Explicit Link Local Flow Control credit management
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