USB IP for UMC

Compare 92 USB IP for UMC from 7 vendors (1 - 10)

Complete USB Type-C Power Delivery PHY, RTL, and Software
- USB PD 3.1 compliant.
- 8 bit register interface for a low speed processor, or optional I2C interface.
- Integrated Chapter 6 protocol reduces required MPU response time to 10mS.
USB 3.0 PHY in UMC (65nm, 40nm)
- Complete mixed-signal physical layer for USB 3.0 applications
- Includes all circuitry needed for operation at all USB speeds (SuperSpeed, High-Speed, FullSpeed, Low-Speed)
- USB-C 3.0 femtoPHY supports Type-C reversible connectors
- Optimized PHY area (<0.5mm2 for USB 3.0, <0.8mm2 for USB-C 3.0)
USB 3.0 femtoPHY in UMC (28nm, 12nm)
- Complete mixed-signal physical layer for USB 3.0 applications
- Includes all circuitry needed for operation at all USB speeds (SuperSpeed, High-Speed, FullSpeed, Low-Speed)
- USB-C 3.0 femtoPHY supports Type-C reversible connectors
- Optimized PHY area (<0.5mm2 for USB 3.0, <0.8mm2 for USB-C 3.0)
USB 2.0 picoPHY in UMC (40nm, 28nm)
- Complete mixed-signal physical layer for single-chip USB 2.0 OTG and non-OTG applications
- Small PHY macro area
- Low power
- Advanced power management features, including support for power supply gating, supply scaling, ultra-low standby current support, and power management unit (PMU) interrupt support
USB 2.0 nanoPHY in UMC (65nm)
- Complete mixed-signal physical layer for single-chip USB 2.0 OTG and non-OTG applications
- Low power: <100mW (during HS packet transmission)
- Small area: ~ 0.6mm2
- High yield—Architecture designed to improve key operating margins by having less sensitivity to variations due to foundry process, chip and board parasitics, and process device model variations
USB 2.0 femtoPHY in UMC (28nm, 22nm)
- Complete mixed-signal physical layer for single-chip USB 2.0 Host, Device, and Dual Role applications Small PHY macro area: as small as 0.20 mm2
- Low power: as low as 50mW (during high-speed packet transmission)
- Advanced power management features including support for power supply gating, supply scaling, ultra-low standby current support, and power management unit (PMU) interrupt support
- Supports USB 2.0 ID-pin detection and OTG Voltage Detectors
USB 3.2 Gen2/Gen1 PHY IP in TSMC(5nm,6nm, 7nm,12nm/16nm, 22nm, 28nm, 40nm, 55nm)
- USB 3.2 Gen2
- 1. Worldwide smallest USB 3.2 Gen2 PHY IP (e.g. IP size @28HPC+ is smaller than 0.7mm²)
- 2. Fully compliant with Universal Serial Bus (USB) 3.2 Gen2 and 2.0 electrical specifications
- 3. Supports clock inputs from 10/12/19.2/24/25/27/30/40MHz crystal oscillator and external clock sources from the core
USB3.2 PHY
- Reference Clock:
- Internal PLL:
- Data Transmit:
- Data Receive:
USB2.0 PHY & Controller
- Compliant with USB Specification Revision 2.0, 1.1
- Configurable 8-bit or 16-bit UTMI interface compliant with UTMI+ Specification Level 3 Revision 1.0
- Supports 480Mbps (HS), 12Mbps (FS) and 1.5Mbps (LS) serial data transmission
- Supports low latency hub mode with 40-bit time round trip delay
USB3.1/3.0 PHY & Controller
- Reference Clock:
- Internal PLL:
- Data Transmit:
- Data Receive: