USB 3.0 PHY IP for TSMC

Welcome to the ultimate USB 3.0 PHY IP for TSMC hub! Explore our vast directory of USB 3.0 PHY IP for TSMC
All offers in USB 3.0 PHY IP for TSMC
Filter
Filter

Login required.

Sign in

Compare 21 USB 3.0 PHY IP for TSMC from 7 vendors (1 - 10)
  • USB3.0 build-in clock PHY, TSMC 55LP
    • Smallest USB 3.2 Gen1x1 BCK PHY IP worldwide (e.g. IP size @40nm <0.36mm²)
    • Fully compliant with Universal Serial Bus USB 3.2 Gen1x1, 2.0, and 1.1 electrical specifications
    • Supports clock outputs from the internal BCK module
    • Real-time calibrations to ensure frequency accuracy
    Block Diagram -- USB3.0 build-in clock PHY, TSMC 55LP
  • USB3.0 build-in clock PHY, TSMC 55LP, type-C
    • Smallest USB 3.2 Gen1x1 BCK PHY IP worldwide (e.g. IP size @40nm <0.36mm²)
    • Fully compliant with Universal Serial Bus USB 3.2 Gen1x1, 2.0, and 1.1 electrical specifications
    • Supports clock outputs from the internal BCK module
    • Real-time calibrations to ensure frequency accuracy
    Block Diagram -- USB3.0 build-in clock PHY, TSMC 55LP, type-C
  • USB3.0 build-in clock PHY, TSMC 22ULP 1.8V, N/S orientation, type-C
    • Smallest USB 3.2 Gen1x1 BCK PHY IP worldwide (e.g. IP size @40nm <0.36mm²)
    • Fully compliant with Universal Serial Bus USB 3.2 Gen1x1, 2.0, and 1.1 electrical specifications
    • Supports clock outputs from the internal BCK module
    • Real-time calibrations to ensure frequency accuracy
    Block Diagram -- USB3.0 build-in clock PHY, TSMC 22ULP 1.8V, N/S orientation, type-C
  • USB3.0 build-in clock PHY, TSMC 22ULL 2.5V, N/S orientation, type-C
    • Smallest USB 3.2 Gen1x1 BCK PHY IP worldwide (e.g. IP size @40nm <0.36mm²)
    • Fully compliant with Universal Serial Bus USB 3.2 Gen1x1, 2.0, and 1.1 electrical specifications
    • Supports clock outputs from the internal BCK module
    • Real-time calibrations to ensure frequency accuracy
    Block Diagram -- USB3.0 build-in clock PHY, TSMC 22ULL 2.5V, N/S orientation, type-C
  • USB3.0 build-in clock PHY, TSMC 22ULL 1.8V, N/S orientation, type-C
    • Smallest USB 3.2 Gen1x1 BCK PHY IP worldwide (e.g. IP size @40nm <0.36mm²)
    • Fully compliant with Universal Serial Bus USB 3.2 Gen1x1, 2.0, and 1.1 electrical specifications
    • Supports clock outputs from the internal BCK module
    • Real-time calibrations to ensure frequency accuracy
    Block Diagram -- USB3.0 build-in clock PHY, TSMC 22ULL 1.8V, N/S orientation, type-C
  • USB 3.0 PHY
    • Standard PHY interface (PIPE) enables multiple IP sources for USB 3.0 Link Layer
    • Supports 5.0 GT=s serial data transmission rate
    • Supports 16- or 32-bit parallel interface
    • Supports PCLK as PHY output
    Block Diagram -- USB 3.0 PHY
  • USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP, Silicon Proven in TSMC 22ULP
    • Compatible with PCIe/USB3/SATA base Specification
    • Fully compatible with PIPE3.1 interface specification
    • Data rate configurable to 1.5G/2.5G/3G/5G/6G for different application
    • Support 16-bit or 32-bit parallel interface when encode/decode enabled
  • USB 3.0 PHY in TSMC (65nm, 55nm, 40nm, 28nm)
    • Complete mixed-signal physical layer for USB 3.0 applications
    • Includes all circuitry needed for operation at all USB speeds (SuperSpeed, High-Speed, FullSpeed, Low-Speed)
    • USB-C 3.0 femtoPHY supports Type-C reversible connectors
    • Optimized PHY area (<0.5mm2 for USB 3.0, <0.8mm2 for USB-C 3.0)
  • USB-C 3.0 femtoPHY in Type-C in TSMC (28nm, 16nm, 12nm)
    • Complete mixed-signal physical layer for USB 3.0 applications
    • Includes all circuitry needed for operation at all USB speeds (SuperSpeed, High-Speed, FullSpeed, Low-Speed)
    • USB-C 3.0 femtoPHY supports Type-C reversible connectors
    • Optimized PHY area (<0.5mm2 for USB 3.0, <0.8mm2 for USB-C 3.0)
  • USB 3.0 femtoPHY in TSMC (28nm, 22nm, 16nm, 12nm)
    • Complete mixed-signal physical layer for USB 3.0 applications
    • Includes all circuitry needed for operation at all USB speeds (SuperSpeed, High-Speed, FullSpeed, Low-Speed)
    • USB-C 3.0 femtoPHY supports Type-C reversible connectors
    • Optimized PHY area (<0.5mm2 for USB 3.0, <0.8mm2 for USB-C 3.0)
×
Semiconductor IP