USB 3.0 IP for TSMC
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USB 3.0 IP
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17
USB 3.0 IP
for TSMC
from 7 vendors
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10)
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A 65nm Wirebond IO library with 1-3.3V GPIO, 3.3V pulse-width modulation cell, I2C & SVID open-drain, 3.3V & 5V analog and OTP program cell
- GPIO:
- I2C / SVID Open-Drain I/O:
- ANALOG
- OTP Programming Cell
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USB 3.0 PHY
- Standard PHY interface (PIPE) enables multiple IP sources for USB 3.0 Link Layer
- Supports 5.0 GT=s serial data transmission rate
- Supports 16- or 32-bit parallel interface
- Supports PCLK as PHY output
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USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP, Silicon Proven in TSMC 22ULP
- Compatible with PCIe/USB3/SATA base Specification
- Fully compatible with PIPE3.1 interface specification
- Data rate configurable to 1.5G/2.5G/3G/5G/6G for different application
- Support 16-bit or 32-bit parallel interface when encode/decode enabled
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USB 3.0 PHY in TSMC (65nm, 55nm, 40nm, 28nm)
- Complete mixed-signal physical layer for USB 3.0 applications
- Includes all circuitry needed for operation at all USB speeds (SuperSpeed, High-Speed, FullSpeed, Low-Speed)
- USB-C 3.0 femtoPHY supports Type-C reversible connectors
- Optimized PHY area (<0.5mm2 for USB 3.0, <0.8mm2 for USB-C 3.0)
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USB-C 3.0 femtoPHY in Type-C in TSMC (28nm, 16nm, 12nm)
- Complete mixed-signal physical layer for USB 3.0 applications
- Includes all circuitry needed for operation at all USB speeds (SuperSpeed, High-Speed, FullSpeed, Low-Speed)
- USB-C 3.0 femtoPHY supports Type-C reversible connectors
- Optimized PHY area (<0.5mm2 for USB 3.0, <0.8mm2 for USB-C 3.0)
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USB 3.0 femtoPHY in TSMC (28nm, 22nm, 16nm, 12nm)
- Complete mixed-signal physical layer for USB 3.0 applications
- Includes all circuitry needed for operation at all USB speeds (SuperSpeed, High-Speed, FullSpeed, Low-Speed)
- USB-C 3.0 femtoPHY supports Type-C reversible connectors
- Optimized PHY area (<0.5mm2 for USB 3.0, <0.8mm2 for USB-C 3.0)
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Single Lane and Quad Lane 5Gbps USB3.1 PHY IP in TSMC 65GP process
- - Parallel data widths of 8bits and 16bits
- - QUAD configuration (4TX and 4RX), Single lane configuration (1TX and 1RX)
- - Support signal loss and receiver detection using programmable multi-tap
- - Support 1m cable
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Single Lane and Quad Lane 5Gbps USB3.1 PHY IP in TSMC 55LP process
- - Parallel data widths of 8bits and 16bits
- - QUAD configuration (4TX and 4RX), Single lane configuration (1TX and 1RX)
- - Support signal loss and receiver detection using programmable multi-tap
- - Support 1m cable
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Single Lane and Quad Lane 5Gbps USB3.1 PHY IP in GF 28SLP process
- - Parallel data widths of 8bits and 16bits
- - QUAD configuration (4TX and 4RX), Single lane configuration (1TX and 1RX)
- - Support signal loss and receiver detection using programmable multi-tap
- - Support 1m cable
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Single Lane and Quad Lane 5Gbps USB3.1 PHY IP in TSMC 28HPC process
- - Parallel data widths of 8bits and 16bits
- - QUAD configuration (4TX and 4RX), Single lane configuration (1TX and 1RX)
- - Support signal loss and receiver detection using programmable multi-tap
- - Support 1m cable