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Multi-Protocol PHY IP for TSMC

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Compare 20 Multi-Protocol PHY IP for TSMC from 4 vendors (1 - 10)
  • MIPI C-PHY/D-PHY Combo DSI RX (Receiver) IP in TSMC 28HPC+
    • Dual mode PHY can support C-PHY and D-PHY
    • Supports MIPI® Specification for D-PHY Version 1.2.
    Block Diagram -- MIPI C-PHY/D-PHY Combo DSI RX (Receiver) IP in TSMC 28HPC+
  • 10Gbps Multi-Protocol PHY IP
    • Supports 10G-KR, PCIe 3.1/2.0/1.0, XAUI, Q/SGMII, and Gigabit Ethernet
    • High-performance decision feedback equalization and adaptive CTLE
    • Available in X1 through X10 lane configurations
    • Bifurcation and inverse bifurcation support
    Block Diagram -- 10Gbps Multi-Protocol PHY IP
  • MIPI C-PHY/D-PHY Combo DSI TX (Transmitter) IP in TSMC 55G
    • Dual mode PHY can support C-PHY and D-PHY
    • Supports MIPI® Specification for D-PHY Version 1.2
    Block Diagram -- MIPI C-PHY/D-PHY Combo DSI TX (Transmitter) IP in TSMC 55G
  • MIPI C-PHY/D-PHY Combo CSI-2 TX (Transmitter) IP in TSMC 65LP
    • Dual mode PHY can support C-PHY and D-PHY
    • Supports MIPI® Specification for D-PHY Version 1.2
    • Backward compatible with MIPI® Specification for D-PHY Version 1.1
    Block Diagram -- MIPI C-PHY/D-PHY Combo CSI-2 TX (Transmitter) IP in TSMC 65LP
  • 224G Ethernet PHY in TSMC (N3E)
    • Optimized for performance, power, and area
    • Includes one, two, or four full-duplex PAM-4/6 transceivers (transmit and receive functions)
    • Supports IEEE and OIF-CEI-224G standards
    • Includes auto-negotiation and link training capabilities
  • 32G PHY in TSMC (N3A) for Automotive
    • Includes one, two, four, eight or sixteen full-duplex transceivers (transmit and receive functions)
    • Supports back channel initialization, aggregation, bifurcation, and power management
    • Supports both internal and external reference clock connections to the PHY
    • Configurable transmitter and receiver equalization, supporting chip-to-chip, port side, backplane interfaces
  • 32G PHY in TSMC (16nm, 12nm, N7, N6, N5, N5A, N3E. N3P)
    • Includes one, two, four, eight or sixteen full-duplex transceivers (transmit and receive functions)
    • Supports back channel initialization, aggregation, bifurcation, and power management
    • Supports both internal and external reference clock connections to the PHY
    • Configurable transmitter and receiver equalization, supporting chip-to-chip, port side, backplane interfaces
  • 56G Ethernet PHY in TSMC (16nm, 12nm)
    • Physical Coding Sublayer (PCS) block with PIPE interface
    • Supports PCIe 6.0 (PAM-4), 5.0, 4.0, 3.1, 2.1, 1.1 encoding, backchannel initialization
    • Supports x1, x2, x4, x8, and x16 hard macro configurations
    • Lane margining at the receiver
  • 12G Ethernet PHY in TSMC (28nm, 16nm, 12nm)
    • Physical Coding Sublayer (PCS) block with PIPE interface
    • Supports PCIe 6.0 (PAM-4), 5.0, 4.0, 3.1, 2.1, 1.1 encoding, backchannel initialization
    • Supports x1, x2, x4, x8, and x16 hard macro configurations
    • Lane margining at the receiver
  • 16G PHY in TSMC (N7) for Automotive
    • Physical Coding Sublayer (PCS) block with PIPE interface
    • Supports PCIe 6.0 (PAM-4), 5.0, 4.0, 3.1, 2.1, 1.1 encoding, backchannel initialization
    • Supports x1, x2, x4, x8, and x16 hard macro configurations
    • Lane margining at the receiver
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