Multi-Protocol PHY IP for TSMC
Welcome to the ultimate Multi-Protocol PHY IP for TSMC hub! Explore our vast directory of Multi-Protocol PHY IP for TSMC
All offers in
Multi-Protocol PHY IP
for TSMC
Filter
Compare
103
Multi-Protocol PHY IP
for TSMC
from 4 vendors
(1
-
10)
-
MIPI C-PHY/D-PHY Combo DSI RX (Receiver) IP in TSMC 28HPC+
- Dual mode PHY can support C-PHY and D-PHY
- Supports MIPI® Specification for D-PHY Version 1.2.
-
10Gbps Multi-Protocol PHY IP
- Supports 10G-KR, PCIe 3.1/2.0/1.0, XAUI, Q/SGMII, and Gigabit Ethernet
- High-performance decision feedback equalization and adaptive CTLE
- Available in X1 through X10 lane configurations
- Bifurcation and inverse bifurcation support
-
MIPI C-PHY/D-PHY Combo DSI TX (Transmitter) IP in TSMC 55G
- Dual mode PHY can support C-PHY and D-PHY
- Supports MIPI® Specification for D-PHY Version 1.2
-
MIPI C-PHY/D-PHY Combo CSI-2 TX (Transmitter) IP in TSMC 65LP
- Dual mode PHY can support C-PHY and D-PHY
- Supports MIPI® Specification for D-PHY Version 1.2
- Backward compatible with MIPI® Specification for D-PHY Version 1.1
-
25G PHY, TSMC N6 x2 North/South (vertical) poly orientation
- Supports 1.25 to 25.8 Gbps data-rate
- Supports PCI Express 4.0 with lane margining, 1G to 100G Ethernet, CCIX, and SATA protocols
- Supports x1 to x16 macro configurations with aggregation and bifurcation
- Spread Spectrum Clock (SSC), ` PCIe Separate Refclk Independent SSC (SRIS) and power management features
-
25G PHY, TSMC 7FF x4 North/South (vertical) poly orientation
- Supports 1.25 to 25.8 Gbps data-rate
- Supports PCI Express 4.0 with lane margining, 1G to 100G Ethernet, CCIX, and SATA protocols
- Supports x1 to x16 macro configurations with aggregation and bifurcation
- Spread Spectrum Clock (SSC), ` PCIe Separate Refclk Independent SSC (SRIS) and power management features
-
25G PHY, TSMC 7FF x2 North/South (vertical) poly orientation
- Supports 1.25 to 25.8 Gbps data-rate
- Supports PCI Express 4.0 with lane margining, 1G to 100G Ethernet, CCIX, and SATA protocols
- Supports x1 to x16 macro configurations with aggregation and bifurcation
- Spread Spectrum Clock (SSC), ` PCIe Separate Refclk Independent SSC (SRIS) and power management features
-
25G PHY, TSMC 7FF x1 North/South (vertical) poly orientation
- Supports 1.25 to 25.8 Gbps data-rate
- Supports PCI Express 4.0 with lane margining, 1G to 100G Ethernet, CCIX, and SATA protocols
- Supports x1 to x16 macro configurations with aggregation and bifurcation
- Spread Spectrum Clock (SSC), ` PCIe Separate Refclk Independent SSC (SRIS) and power management features
-
25G MR Ethernet PHY, TSMC 7FF x4 North/South (vertical) poly orientation
- Supports 1.25 to 25.8 Gbps data-rate
- Supports PCI Express 4.0 with lane margining, 1G to 100G Ethernet, CCIX, and SATA protocols
- Supports x1 to x16 macro configurations with aggregation and bifurcation
- Spread Spectrum Clock (SSC), ` PCIe Separate Refclk Independent SSC (SRIS) and power management features
-
25G MR Ethernet PHY, TSMC 7FF x2 North/South (vertical) poly orientation
- Supports 1.25 to 25.8 Gbps data-rate
- Supports PCI Express 4.0 with lane margining, 1G to 100G Ethernet, CCIX, and SATA protocols
- Supports x1 to x16 macro configurations with aggregation and bifurcation
- Spread Spectrum Clock (SSC), ` PCIe Separate Refclk Independent SSC (SRIS) and power management features