IP Catalog > Foundries > TSMC > Interface IP > Interconnect IP > Ethernet IP

Ethernet IP for TSMC

Welcome to the ultimate Ethernet IP for TSMC hub! Explore our vast directory of Ethernet IP for TSMC
All offers in Ethernet IP for TSMC
Filter
Filter

Login required.

Sign in

Login required.

Sign in

Search (22)
Compare 22 Ethernet IP for TSMC from 6 vendors (1 - 10)
  • 1G Deep Buffering Memory Ethernet Switch IP Core
    • Delivers Performance
    • Highly Configurable
    • Easy to use
    • Silicon Agnostic
    Block Diagram -- 1G Deep Buffering Memory Ethernet Switch IP Core
  • 224G Ethernet PHY, TSMC N3P x1, North/South (vertical) poly orientation
    • Supports full-duplex 1.25 to 224Gbps data rates
    • Enables 200G, 400G, 800G, and 1.6T Ethernet
    • Ethernet interconnects for wired network infrastructure
    • Supports IEEE 802.3 and OIF-224G standards electrical specifications
    Block Diagram -- 224G Ethernet PHY, TSMC N3P x1, North/South (vertical) poly orientation
  • 224G Ethernet PHY, TSMC N3E x4, North/South (vertical) poly orientation
    • Supports full-duplex 1.25 to 224Gbps data rates
    • Enables 200G, 400G, 800G, and 1.6T Ethernet
    • Ethernet interconnects for wired network infrastructure
    • Supports IEEE 802.3 and OIF-224G standards electrical specifications
    Block Diagram -- 224G Ethernet PHY, TSMC N3E x4, North/South (vertical) poly orientation
  • 112G PHY, TSMC N7 x4, North/South (vertical) poly orientation
    • Supports full-duplex 1.25 to 112Gbps data rates in several lane configurations
    • Enables 100G, 200G, 400G, 800G Ethernet interconnects for wired and optical network infrastructure
    • Supports IEEE 802.3ck and OIF standards electrical specifications
    • Meets the performance requirements of multi-die, co-packaged optics, near-packaged optics, chip-to-chip, chip-to-module, and backplane interconnects
    Block Diagram -- 112G PHY, TSMC N7 x4, North/South (vertical) poly orientation
  • 112G Ethernet PHY, TSMC N7 x4, North/South (vertical) poly orientation
    • Supports full-duplex 1.25 to 112Gbps data rates in several lane configurations
    • Enables 100G, 200G, 400G, 800G Ethernet interconnects for wired and optical network infrastructure
    • Supports IEEE 802.3ck and OIF standards electrical specifications
    • Meets the performance requirements of multi-die, co-packaged optics, near-packaged optics, chip-to-chip, chip-to-module, and backplane interconnects
    Block Diagram -- 112G Ethernet PHY, TSMC N7 x4, North/South (vertical) poly orientation
  • 112G Ethernet PHY, TSMC N7 x2, North/South (vertical) poly orientation
    • Supports full-duplex 1.25 to 112Gbps data rates in several lane configurations
    • Enables 100G, 200G, 400G, 800G Ethernet interconnects for wired and optical network infrastructure
    • Supports IEEE 802.3ck and OIF standards electrical specifications
    • Meets the performance requirements of multi-die, co-packaged optics, near-packaged optics, chip-to-chip, chip-to-module, and backplane interconnects
    Block Diagram -- 112G Ethernet PHY, TSMC N7 x2, North/South (vertical) poly orientation
  • 112G Ethernet PHY, TSMC N7 x1, North/South (vertical) poly orientation
    • Supports full-duplex 1.25 to 112Gbps data rates in several lane configurations
    • Enables 100G, 200G, 400G, 800G Ethernet interconnects for wired and optical network infrastructure
    • Supports IEEE 802.3ck and OIF standards electrical specifications
    • Meets the performance requirements of multi-die, co-packaged optics, near-packaged optics, chip-to-chip, chip-to-module, and backplane interconnects
    Block Diagram -- 112G Ethernet PHY, TSMC N7 x1, North/South (vertical) poly orientation
  • 112G Ethernet PHY, TSMC N6 x2, North/South (vertical) poly orientation
    • Supports full-duplex 1.25 to 112Gbps data rates in several lane configurations
    • Enables 100G, 200G, 400G, 800G Ethernet interconnects for wired and optical network infrastructure
    • Supports IEEE 802.3ck and OIF standards electrical specifications
    • Meets the performance requirements of multi-die, co-packaged optics, near-packaged optics, chip-to-chip, chip-to-module, and backplane interconnects
    Block Diagram -- 112G Ethernet PHY, TSMC N6 x2, North/South (vertical) poly orientation
  • 112G Ethernet PHY, TSMC N6 x1, North/South (vertical) poly orientation
    • Supports full-duplex 1.25 to 112Gbps data rates in several lane configurations
    • Enables 100G, 200G, 400G, 800G Ethernet interconnects for wired and optical network infrastructure
    • Supports IEEE 802.3ck and OIF standards electrical specifications
    • Meets the performance requirements of multi-die, co-packaged optics, near-packaged optics, chip-to-chip, chip-to-module, and backplane interconnects
    Block Diagram -- 112G Ethernet PHY, TSMC N6 x1, North/South (vertical) poly orientation
  • 112G Ethernet PHY, TSMC N5 x4, North/South (vertical) poly orientation
    • Supports full-duplex 1.25 to 112Gbps data rates in several lane configurations
    • Enables 100G, 200G, 400G, 800G Ethernet interconnects for wired and optical network infrastructure
    • Supports IEEE 802.3ck and OIF standards electrical specifications
    • Meets the performance requirements of multi-die, co-packaged optics, near-packaged optics, chip-to-chip, chip-to-module, and backplane interconnects
    Block Diagram -- 112G Ethernet PHY, TSMC N5 x4, North/South (vertical) poly orientation
×
Semiconductor IP