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Broadcast IP for TSMC

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Compare 14 Broadcast IP for TSMC from 10 vendors (1 - 10)
  • VESA DisplayPort 1.4 RX IP Subsystem for Xilinx FPGAs
    • Complete DisplayPort™ 1.4 Receiver solution with support for VESA Display Stream Compression (DSC)
    Block Diagram -- VESA DisplayPort 1.4 RX IP Subsystem for Xilinx FPGAs
  • Fully Configurable Radix 2 FFT/IFFT Processor
    • Radix-2 Fast Fourier Transform processor IP Core.
    • Same IP core may be used to compute both FFT and IFFT transforms without any complexity overhead.
    • Highly parameterizable/scalable design using generic I/O fixed point precision and generic internal calculations precision.
    • Bit true Matlab script model is provided to aid core fixed point precision configuration for any target application.
    Block Diagram -- Fully Configurable Radix 2 FFT/IFFT Processor
  • ITU G.704 E1 Framer/Deframer
    • E1 framer/deframer compliant to G.704, G.706, G.732 and O.163 ITU recommendations.
    • Supports CAS and CCS signalling standards.
    • Supports CRC4 based framing standards.
    • User configurable receive and transmit control.
    Block Diagram -- ITU G.704 E1 Framer/Deframer
  • ISDB-T1, Segment Tuner (470-860MHz UHF)
    • High Performance
    • Configurable 3/4 wire controller
    • Self calibrating and programmable filter corner frequencies
    • 8 Bit electronically tunable tracking filter
    Block Diagram -- ISDB-T1, Segment Tuner (470-860MHz UHF)
  • 12-bit 250MHz interpolation filter with 43 taps
    • Programmable Coefficients
    • Programmable gain/attenuation at the output
    • 4X Decimation Factor
  • 12-bit 250MHz Decimation filter with 43 taps
    • Programmable Coefficients
    • Programmable gain/attenuation at the output
    • 4X Decimation Factor
  • Fast Fourier Transformation
    • The FFT is a fully customizable FFT. The key features are free choose of the FFT dimension, data width and an additional output with the absolute value of the spectrum.
  • SPDIF-Tx-Pro : Configurable SPDIF/AES3 Transmitter
    • Supports the IEC60958 (SPDIF) and AES3 standards for PCM audio transmission
    • Supports the IEC61937, SMPTE 337M standards for non-PCM audio transmission
    • Automatic insertion of Validity bits in non-PCM mode
    • Supports any sample rate Fs by setting the audio clock frequency to 256*Fs including 32, 44.1, 48, 96 and 192 kHz
  • SPDIF-Rx-Pro : Configurable SPDIF-AES/EBU Receiver
    • Supports the IEC60958 (SPDIF), AES3 standards for PCM audio transmission
    • Supports the IEC61937, SMPTE 337M standards for non-PCM (ie, compressed) audio transmission
    • Uses a single domain clock frequency, unrelated to the sample frequency
    • Supports up to 24 bits per sample
  • AR4JA LDPC Decoder
    • AR4JA LDPC code family is quasi-cyclic.
    • Irregular parity check matrix.
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