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USB 3.0 PHY IP for SMIC

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Compare 14 USB 3.0 PHY IP for SMIC from 8 vendors (1 - 10)
  • USB3.0 build-in clock PHY, SMIC 55LL
    • Smallest USB 3.2 Gen1x1 BCK PHY IP worldwide (e.g. IP size @40nm <0.36mm²)
    • Fully compliant with Universal Serial Bus USB 3.2 Gen1x1, 2.0, and 1.1 electrical specifications
    • Supports clock outputs from the internal BCK module
    • Real-time calibrations to ensure frequency accuracy
    Block Diagram -- USB3.0 build-in clock PHY, SMIC 55LL
  • USB 3.0 PHY
    • Standard PHY interface (PIPE) enables multiple IP sources for USB 3.0 Link Layer
    • Supports 5.0 GT=s serial data transmission rate
    • Supports 16- or 32-bit parallel interface
    • Supports PCLK as PHY output
    Block Diagram -- USB 3.0 PHY
  • USB 3.0 PHY in SMIC (110nm, 65nm, 40nm)
    • Complete mixed-signal physical layer for USB 3.0 applications
    • Includes all circuitry needed for operation at all USB speeds (SuperSpeed, High-Speed, FullSpeed, Low-Speed)
    • USB-C 3.0 femtoPHY supports Type-C reversible connectors
    • Optimized PHY area (<0.5mm2 for USB 3.0, <0.8mm2 for USB-C 3.0)
  • USB 3.0 femtoPHY in SMIC (28nm)
    • Complete mixed-signal physical layer for USB 3.0 applications
    • Includes all circuitry needed for operation at all USB speeds (SuperSpeed, High-Speed, FullSpeed, Low-Speed)
    • USB-C 3.0 femtoPHY supports Type-C reversible connectors
    • Optimized PHY area (<0.5mm2 for USB 3.0, <0.8mm2 for USB-C 3.0)
  • PCIe 3.0/3.1/USB3.0/SATA3 Combo PHY
    • Standard PHY interface enables multiple IP sources for PCI Express Logical Layer and provides a target interface for PCI Express PHY vendors.
    • Supports 2.5Gb/s only or 2.5Gb/s,5.0Gb/s and 8.0Gb/s serial data transmission rate
    • Utilizes 8-bit, 16-bit or 32- bit parallel interface to transmit and receive PCI Express data
    • Allows integration of high speed components into a single functional block as seen by the endpoint device designer.
  • SMIC 28nm USB3.0 Dual Role PHY/Type-C
    • 5-Gbps SuperSpeed data transmission rate through 3-m USB3.0 cable
  • CSMC 0.13um USB 1.1 PHY
    • Complies with the USB1.1 standard
    • CSMC 0.13um, 1.2v/3.3v power supply, 1P6M logic process
    • Uses digital input/output to transmit or receive USB cable data
    • Supports 12Mbit/s full speed and 1.5Mbit/s low speed serial data transmission
  • SMIC 65nm USB2.0 Dual Role PHY
    • Process: SMIC 65nm LL process
    • Supply voltage: 1.08v~1.2v~1.32v, 2.25v~2.5v~2.75v, 2.97v~3.3v~3.63v
    • Compliant with the USB Spec Rev2.0
    • Compliant with the UTMI Spec Rev1.05
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