USB IP for SMIC

USB PD 3.1 compliant.
Single chip solution – just two external capacitors.
4 pin package.
Less than 1mm2 area in 180nm.
PROM programmed through vendor message protocol.
Based on Obsidian’s mature PD technology.
Integrated PROM enables customized response to a wide range of vendor requirements.
Active Ra pulls down only requires 10uA at 5V., but is <1K below 2V.
Power <5mW. Enabled by CC data activity. I.e. very low duty cycle.
Programming can be done after assembly into the cable. Fuse lock function.
Supports low cost, 4 layer PCB assembly.

Mixed signal Analog Front End Macros for 65n, 130n, 150nm, and 180n technologies.
RTL code from AFE to I2C compatible register set.
Stand alone C code for Protocol, Device Policy Manager, and System Policy Manager.
IP demonstration & development board, with compliance reports.
Full chip integration of USB Type-C, and associated software.

Ported to over 50 different processes and configurations ranging from 65-nm to 14/16-nm FinFET
Supports the USB 2.0 protocol and data rate (480 Mbps)
Supports the USB Type-C specification
USB femtoPHY, USB nanoPHY and USB picoPHY offer a tunability feature that allows quick, post-silicon adjustments that occur due to process variations, or unexpected chip and board parasitic, without modifying the existing design

Ported to over 50 different processes and configurations ranging from 65-nm to 14/16-nm FinFET
Supports the USB 2.0 protocol and data rate (480 Mbps)
Supports the USB Type-C specification
USB femtoPHY, USB nanoPHY and USB picoPHY offer a tunability feature that allows quick, post-silicon adjustments that occur due to process variations, or unexpected chip and board parasitic, without modifying the existing design

Smallest USB 3.2 Gen1x1 BCK PHY IP worldwide (e.g. IP size @40nm <0.36mm²)
Fully compliant with Universal Serial Bus USB 3.2 Gen1x1, 2.0, and 1.1 electrical specifications
Supports clock outputs from the internal BCK module
Real-time calibrations to ensure frequency accuracy

Smallest USB 3.2 Gen1x1 BCK PHY IP worldwide (e.g. IP size @40nm <0.36mm²)
Fully compliant with Universal Serial Bus USB 3.2 Gen1x1, 2.0, and 1.1 electrical specifications
Supports clock outputs from the internal BCK module
Real-time calibrations to ensure frequency accuracy

Smallest USB 3.2 Gen1x1 BCK PHY IP worldwide (e.g. IP size @40nm <0.36mm²)
Fully compliant with Universal Serial Bus USB 3.2 Gen1x1, 2.0, and 1.1 electrical specifications
Supports clock outputs from the internal BCK module
Real-time calibrations to ensure frequency accuracy

Smallest USB 3.2 Gen1x1 BCK PHY IP worldwide (e.g. IP size @40nm <0.36mm²)
Fully compliant with Universal Serial Bus USB 3.2 Gen1x1, 2.0, and 1.1 electrical specifications
Supports clock outputs from the internal BCK module
Real-time calibrations to ensure frequency accuracy

Standard PHY interface (PIPE) enables multiple IP sources for USB 3.0 Link Layer
Supports 5.0 GT=s serial data transmission rate
Supports 16- or 32-bit parallel interface
Supports PCLK as PHY output

Complete mixed-signal physical layer for single-chip USB 2.0 OTG and non-OTG applications
Low power: <100mW (during HS packet transmission)
Small area: ~ 0.6mm2
High yield—Architecture designed to improve key operating margins by having less sensitivity to variations due to foundry process, chip and board parasitics, and process device model variations