USB IP for SMIC

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Compare 52 USB IP for SMIC from 10 vendors (1 - 10)
  • Complete USB Type-C Power Delivery PHY, RTL, and Software
    • USB PD 3.1 compliant.
    • 8 bit register interface for a low speed processor, or optional I2C interface.
    • Integrated Chapter 6 protocol reduces required MPU response time to 10mS.
    Block Diagram -- Complete USB Type-C Power Delivery  PHY, RTL, and Software
  • USB 2.0 femtoPHY - SMIC 28PS18 x1, North/South (vertical) poly orientation
    • Ported to over 50 different processes and configurations ranging from 65-nm to 14/16-nm FinFET
    • Supports the USB 2.0 protocol and data rate (480 Mbps)
    • Supports the USB Type-C specification
    • USB femtoPHY, USB nanoPHY and USB picoPHY offer a tunability feature that allows quick, post-silicon adjustments that occur due to process variations, or unexpected chip and board parasitic, without modifying the existing design
    Block Diagram -- USB 2.0 femtoPHY - SMIC 28PS18 x1, North/South (vertical) poly orientation
  • USB 2.0 femtoPHY - SMIC 28HKMG18 x1, OTG, North/South (vertical) poly orientation
    • Ported to over 50 different processes and configurations ranging from 65-nm to 14/16-nm FinFET
    • Supports the USB 2.0 protocol and data rate (480 Mbps)
    • Supports the USB Type-C specification
    • USB femtoPHY, USB nanoPHY and USB picoPHY offer a tunability feature that allows quick, post-silicon adjustments that occur due to process variations, or unexpected chip and board parasitic, without modifying the existing design
    Block Diagram -- USB 2.0 femtoPHY - SMIC 28HKMG18 x1, OTG, North/South (vertical) poly orientation
  • USB1.1 build-in clock PHY, SMIC 55LL
    • Smallest USB 3.2 Gen1x1 BCK PHY IP worldwide (e.g. IP size @40nm <0.36mm²)
    • Fully compliant with Universal Serial Bus USB 3.2 Gen1x1, 2.0, and 1.1 electrical specifications
    • Supports clock outputs from the internal BCK module
    • Real-time calibrations to ensure frequency accuracy
    Block Diagram -- USB1.1 build-in clock PHY, SMIC 55LL
  • USB2.0 build-in clock PHY, SMIC 55LL
    • Smallest USB 3.2 Gen1x1 BCK PHY IP worldwide (e.g. IP size @40nm <0.36mm²)
    • Fully compliant with Universal Serial Bus USB 3.2 Gen1x1, 2.0, and 1.1 electrical specifications
    • Supports clock outputs from the internal BCK module
    • Real-time calibrations to ensure frequency accuracy
    Block Diagram -- USB2.0 build-in clock PHY, SMIC 55LL
  • USB2.0 build-in clock PHY, SMIC 40LL, type-C
    • Smallest USB 3.2 Gen1x1 BCK PHY IP worldwide (e.g. IP size @40nm <0.36mm²)
    • Fully compliant with Universal Serial Bus USB 3.2 Gen1x1, 2.0, and 1.1 electrical specifications
    • Supports clock outputs from the internal BCK module
    • Real-time calibrations to ensure frequency accuracy
    Block Diagram -- USB2.0 build-in clock PHY, SMIC 40LL, type-C
  • USB3.0 build-in clock PHY, SMIC 55LL
    • Smallest USB 3.2 Gen1x1 BCK PHY IP worldwide (e.g. IP size @40nm <0.36mm²)
    • Fully compliant with Universal Serial Bus USB 3.2 Gen1x1, 2.0, and 1.1 electrical specifications
    • Supports clock outputs from the internal BCK module
    • Real-time calibrations to ensure frequency accuracy
    Block Diagram -- USB3.0 build-in clock PHY, SMIC 55LL
  • USB 3.0 PHY
    • Standard PHY interface (PIPE) enables multiple IP sources for USB 3.0 Link Layer
    • Supports 5.0 GT=s serial data transmission rate
    • Supports 16- or 32-bit parallel interface
    • Supports PCLK as PHY output
    Block Diagram -- USB 3.0 PHY
  • USB 2.0 nanoPHY in SMIC (65nm)
    • Complete mixed-signal physical layer for single-chip USB 2.0 OTG and non-OTG applications
    • Low power: <100mW (during HS packet transmission)
    • Small area: ~ 0.6mm2
    • High yield—Architecture designed to improve key operating margins by having less sensitivity to variations due to foundry process, chip and board parasitics, and process device model variations
  • USB 3.0 PHY in SMIC (110nm, 65nm, 40nm)
    • Complete mixed-signal physical layer for USB 3.0 applications
    • Includes all circuitry needed for operation at all USB speeds (SuperSpeed, High-Speed, FullSpeed, Low-Speed)
    • USB-C 3.0 femtoPHY supports Type-C reversible connectors
    • Optimized PHY area (<0.5mm2 for USB 3.0, <0.8mm2 for USB-C 3.0)
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