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DDR5 IP for Samsung

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Compare 24 DDR5 IP for Samsung from 4 vendors (1 - 10)
  • LPDDR5X/5/4X/4 combo PHY at Samsung SF5A
    • Compliant for JEDEC standards for LPDDR5X/5/4X/4 with PHY standards
    • DFI 5.1 specification PHY Interface Compliant
    • Support up to 4 ranks
    • x16 and x32 channel support
    Block Diagram -- LPDDR5X/5/4X/4 combo PHY at Samsung SF5A
  • DDR5/4 PHY for Samsung
    • Lowest latency for data-intensive applications
    • Highest data rates with detailed system guidelines
    Block Diagram -- DDR5/4 PHY for Samsung
  • GDDR6 PHY for Samsung
    • Derived from Cadence’s silicon-proven DDR, LPDDR, and high-speed SerDes designs
    • Highest data rates with detailed system guidelines
    Block Diagram -- GDDR6 PHY for Samsung
  • DDR5/4 PHY V2C CU - SS SF4X
    • Supports JEDEC standard DDR5 and DDR4 SDRAMs
    • High-performance DDR PHY supporting data rates up to 8400 Mbps
    • PHY independent, firmware-based training using an embedded calibration processor
    • Supports up to 4 trained states/ frequencies with <3μs switching time
    Block Diagram -- DDR5/4 PHY V2C CU - SS SF4X
  • DDR5/4 PHY V2 - SS 8LPU
    • Supports JEDEC standard DDR5 and DDR4 SDRAMs
    • High-performance DDR PHY supporting data rates up to 8400 Mbps
    • PHY independent, firmware-based training using an embedded calibration processor
    • Supports up to 4 trained states/ frequencies with <3μs switching time
    Block Diagram -- DDR5/4 PHY V2 - SS 8LPU
  • DDR5/4 PHY - SS 7LPP
    • Supports JEDEC standard DDR5 and DDR4 SDRAMs
    • High-performance DDR PHY supporting data rates up to 8400 Mbps
    • PHY independent, firmware-based training using an embedded calibration processor
    • Supports up to 4 trained states/ frequencies with <3μs switching time
    Block Diagram -- DDR5/4 PHY - SS 7LPP
  • DDR5/4 PHY - SS 10LPP
    • Supports JEDEC standard DDR5 and DDR4 SDRAMs
    • High-performance DDR PHY supporting data rates up to 8400 Mbps
    • PHY independent, firmware-based training using an embedded calibration processor
    • Supports up to 4 trained states/ frequencies with <3μs switching time
    Block Diagram -- DDR5/4 PHY - SS 10LPP
  • DDR5 PHY - SS SF4X
    • Supports JEDEC standard DDR5 and DDR4 SDRAMs
    • High-performance DDR PHY supporting data rates up to 8400 Mbps
    • PHY independent, firmware-based training using an embedded calibration processor
    • Supports up to 4 trained states/ frequencies with <3μs switching time
    Block Diagram -- DDR5 PHY - SS SF4X
  • LPDDR4X multiPHY in Samsung (14nm, 11nm)
    • Low latency, small area, low power
    • Compatible with JEDEC standard LPDDR4 SDRAMs up to 4,267 Mbps
    • Maximum data rate is process technology dependent
    • Compatible with JEDEC standard DDR4 SDRAMs up to 3,200 Mbps
  • LPDDR4 multiPHY V2 in Samsung (8nm) for Automotive
    • Low latency, small area, low power
    • Compatible with JEDEC standard LPDDR4 SDRAMs up to 4,267 Mbps
    • Maximum data rate is process technology dependent
    • Compatible with JEDEC standard DDR4 SDRAMs up to 3,200 Mbps
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