Memory Interface IP for GLOBALFOUNDRIES

Compare 31 Memory Interface IP for GLOBALFOUNDRIES from 7 vendors (1 - 10)

LPDDR5T / LPDDR5X / LPDDR5 Controller
- Support for all LPDDR5T/5X/5 devices
- Bank management logic monitors status of each bank
- Queue-based user interface with reordering scheduler
- Look-ahead activate, precharge, and auto-precharge logic
- Parity protection for all stored control registers
- PHY interface based on DFI 5.1 standard
DDR PHY
- DDR5/4/3 training with write-leveling and data-eye training
- Optional clock gating available for low-power control
- Internal and external datapath loop-back modes
- I/O pads with impedance calibration logic and data retention capability
- Programmable per-bit (PVT compensated) deskew on read and write datapaths
- RX and TX equalization for heavily loaded systems
SATA PHY
- Serial ATA II Revision 2.6 compliant
- Gen1i, Gen1m, Gen2i, Gen2m compliant
- Gen1x, Gen2x compatible
- Initialization and power saving modes
LPDDR5/4/4X PHY - GF 12LP+ for Automotive ASIL B Random, AEC-Q100 Grade 1
- Supports JEDEC standard LPDDR5X, LPDDR5, LPDDR4 and LPDDR4X SDRAMs
- Support for data rates up to 6400 Mbps
- Designed for rapid integration with Synopsys’ LPDDR5/4/4X controller for a complete DDR interface solution
- DFI 5.0 controller interface
LPDDR5/4/4X PHY - GF 12LP+
- Supports JEDEC standard LPDDR5X, LPDDR5, LPDDR4 and LPDDR4X SDRAMs
- Support for data rates up to 6400 Mbps
- Designed for rapid integration with Synopsys’ LPDDR5/4/4X controller for a complete DDR interface solution
- DFI 5.0 controller interface
DDR5/4 PHY - GF 12LP+
- Supports JEDEC standard DDR5 and DDR4 SDRAMs
- High-performance DDR PHY supporting data rates up to 8400 Mbps
- PHY independent, firmware-based training using an embedded calibration processor
- Supports up to 4 trained states/ frequencies with <3μs switching time
Bi-directional High speed interface lane up to 12.5Gbps
- High data rate (Up to 12.5Gbps per lane)
- Programmable receiver frontend
- Programmable transmitter
- 5-bit controlled digital delay line in the receiver for high-speed clock
SATA 6G PHY in GF (40nm, 28nm)
- Compliant with SATA/eSATA v3.3, AHCI v1.3 and SATA PIPE v4.3 specifications
- AMBA 2.0 AHB and AMBA 3 AXI subsystem interfaces
- AMBA 4 AXI and ACE-Lite bus interfaces
- Memory data protection and memory address parity protection
LPDDR5/4/4X PHY in GF (12nm)
- Low latency, small area, low power
- Compatible with JEDEC standard LPDDR5 SDRAMs up to 6400 Mbps
- Compatible with JEDEC standard LPDDR4 and LPDDR4X SDRAMs up to 4267 Mbps
- DFI 5.0 compliant interface to the memory controller
LPDDR4X multiPHY Plus in GF (12nm)
- Low latency, small area, low power
- Compatible with JEDEC standard LPDDR4 SDRAMs up to 4,267 Mbps
- Maximum data rate is process technology dependent
- Compatible with JEDEC standard DDR4 SDRAMs up to 3,200 Mbps