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USB IP for GLOBALFOUNDRIES

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Compare 21 USB IP for GLOBALFOUNDRIES from 7 vendors (1 - 10)
  • Complete USB Type-C Power Delivery PHY, RTL, and Software
    • USB PD 3.1 compliant.
    • 8 bit register interface for a low speed processor, or optional I2C interface.
    • Integrated Chapter 6 protocol reduces required MPU response time to 10mS.
    Block Diagram -- Complete USB Type-C Power Delivery PHY, RTL, and Software
  • USB-C 3.1/DP TX PHY in GF (22nm)
    • Lowest risk: Based on proven USB 3.0 controller shipped in 100s of millions of units
    • Lowest power: Extend battery life in mobile devices (USB power saving modes, Uniform Power Format, hibernation option with dual power rails)
    • Configurable data buffering options to optimize performance vs area
    • Supports all USB speed modes
  • USB 3.1 PHY (10G/5G) in GF (22nm)
    • Lowest risk: Based on proven USB 3.0 controller shipped in 100s of millions of units
    • Lowest power: Extend battery life in mobile devices (USB power saving modes, Uniform Power Format, hibernation option with dual power rails)
    • Configurable data buffering options to optimize performance vs area
    • Supports all USB speed modes
  • USB 3.0 SSPHY in GF (22nm)
    • Complete mixed-signal physical layer for USB 3.0 applications
    • Includes all circuitry needed for operation at all USB speeds (SuperSpeed, High-Speed, FullSpeed, Low-Speed)
    • USB-C 3.0 femtoPHY supports Type-C reversible connectors
    • Optimized PHY area (<0.5mm2 for USB 3.0, <0.8mm2 for USB-C 3.0)
  • USB 2.0 picoPHY in GF (40nm, 28nm)
    • Complete mixed-signal physical layer for single-chip USB 2.0 OTG and non-OTG applications
    • Small PHY macro area
    • Low power
    • Advanced power management features, including support for power supply gating, supply scaling, ultra-low standby current support, and power management unit (PMU) interrupt support
  • USB 2.0 nanoPHY in GF (55nm)
    • Complete mixed-signal physical layer for single-chip USB 2.0 OTG and non-OTG applications
    • Low power: <100mW (during HS packet transmission)
    • Small area: ~ 0.6mm2
    • High yield—Architecture designed to improve key operating margins by having less sensitivity to variations due to foundry process, chip and board parasitics, and process device model variations
  • USB 2.0 femtoPHY in GF (28nm, 22nm, 12nm)
    • Complete mixed-signal physical layer for single-chip USB 2.0 Host, Device, and Dual Role applications Small PHY macro area: as small as 0.20 mm2
    • Low power: as low as 50mW (during high-speed packet transmission)
    • Advanced power management features including support for power supply gating, supply scaling, ultra-low standby current support, and power management unit (PMU) interrupt support
    • Supports USB 2.0 ID-pin detection and OTG Voltage Detectors
  • USB 2.0 femtoPHY in GF (22nm) for Automotive Grade 1
    • Complete mixed-signal physical layer for single-chip USB 2.0 Host, Device, and Dual Role applications Small PHY macro area: as small as 0.20 mm2
    • Low power: as low as 50mW (during high-speed packet transmission)
    • Advanced power management features including support for power supply gating, supply scaling, ultra-low standby current support, and power management unit (PMU) interrupt support
    • Supports USB 2.0 ID-pin detection and OTG Voltage Detectors
  • USB 3.0 PHY in GF (65nm, 55nm, 40nm, 28nm)
    • Complete mixed-signal physical layer for USB 3.0 applications
    • Includes all circuitry needed for operation at all USB speeds (SuperSpeed, High-Speed, FullSpeed, Low-Speed)
    • USB-C 3.0 femtoPHY supports Type-C reversible connectors
    • Optimized PHY area (<0.5mm2 for USB 3.0, <0.8mm2 for USB-C 3.0)
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