PCI IP for GLOBALFOUNDRIES
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PCI IP
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19
PCI IP
for GLOBALFOUNDRIES
from 7 vendors
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10)
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PCIe Gen2 PHY
- PCI Express Gen 2 and Gen 1 compliant
- Supports various PCI Express modes and extensions
- Programmable amplitude and pre-emphasis
- Programmable receiver equalization
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PCIe Gen3 PHY
- Low Risk - Silicon proven with Si characterization data
- Excellent Interoperability
- Superior Noise Immunity
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PCIe 3.0, 2.1, 1.1 Controller with the PHY Interface for PCI Express (PIPE) specification and native user interface support
- Complies with the PCI Express® Base 3.0 Specification, rev.3.1
- Supports Endpoint, Root-Port, Dual-Role, Switch configurations
- Supports x16, x8, x4, x2, x1 at Gen3, Gen2, Gen1 speeds
- Implements one Virtual Channel
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PCIe 3.0, 2.1, 1.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with AMBA AXI User Interface
- PCIe Interface
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Bi-directional High speed interface lane up to 12.5Gbps
- High data rate (Up to 12.5Gbps per lane)
- Programmable receiver frontend
- Programmable transmitter
- 5-bit controlled digital delay line in the receiver for high-speed clock
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PCIe 4.0 PHY in GF (14nm, 12nm)
- Physical Coding Sublayer (PCS) block with PIPE interface
- Support PCIe 4.0, 3.1, 2.1, 1.1 encoding, backchannel initialization
- Lane margining at the receiver
- Spread-spectrum clocking (SRIS)
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PCIe 3.0 PHY in GF (28nm)
- Physical coding sublayer (PCS) block with PIPE interface
- Supports PCIe 3.1, 2.1, 1.1 encoding, backchannel initialization
- Spread-spectrum clocking (SRIS)
- Supports PCIe power management features, including L1 substate; power gating and power island; DFE bypass option and voltage mode Tx with under drive supply options
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PCIe 2.0 PHY in GF (40nm, 28nm, 22nm, 12nm)
- Physical coding sublayer (PCS) block with PIPE interface
- Supports PCIe power management features, including L1 substate
- Power gating for lowest standby power
- Low active power using voltage mode TX with under drive supply options