V-By-One Receiver_8ch

Overview

Innosilicon VBO RX IP is designed to receive and recover the video data from a VBO source device for display applications.
Innosilicon VBO RX IP is composed of physical layer and digital controller. The physical layer contains 8 data lanes and bias circuit. The data lane consists of termination, equalizer and CDR circuit. In each data lane, the termination provides common mode voltage and termination resistance for the differential pair at the receiver end. The equalizer firstly changes the common mode voltage of input signals from the termination supply domain to a proper level that satisfies the input voltage range of equalizer. Then the input signals are reshaped by equalizer for frequency compensation. Finally, the serial stream is recovered by CDR and converted to 10-bit parallel output. The bias circuit generates voltage and current reference.
The digital controller contains 8 data process paths to deal with the recovered video data. Each path consists of 10b/8b decoder, descrambler and 3/4/5-byte unpacker. The recovered video data are finally converted to 40-bit video data, 24-bit control data and timing data.
Innosilicon VBO RX IP offers reliable implementation for VBO interface, which can be integrated in the SOC used in multimedia device.

Key Features

  • Area: 1.224mm2 (1440um x 850um) including IO and ESD
  • Compliant with V-By-One HS 1.4 standard
  • Support 1/2/4/8-lane configuration
  • Support 3/4/5-byte mode
  • Support data rate up to 4Gbps per lane
  • Support display resolution up to 4K/60Hz
  • Support AC-coupled input and termination connected to ground
  • Support programmable termination, equalizer and CDR dynamics
  • Support automatic termination resistance
  • Support BIST logic
  • Typical 27MHz reference clock
  • APB slave interface for internal register access
  • Built-in bandgap reference

Benefits

  • Low power consumption
  • Fully customizable
  • Small area
  • Simple integration process
  • Available options include:
    • Test chips and test boards
    • FPGA integration support
    • Chip level integration support

Deliverables

  • Datasheet
  • Encrypted Verilog Model
  • Timing Library Model (LIB)
  • Library Exchange Format (LEF)
  • GDSII Database
  • Evaluation Board if Available

Technical Specifications

Foundry, Node
TSMC 55/40/12nm, GF 22nm
GLOBALFOUNDRIES
In Production: 22nm FDX
TSMC
In Production: 12nm , 40nm G , 40nm LP , 55nm LP
UMC
In Production: 40nm
Silicon Proven: 40nm
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Semiconductor IP