Successive Approximation ADC_2M12b
Overview
Innosilicon SAR-ADC IP is a small-size, low power analog to digital converter. The converter is a charge-redistribution successive approximation ADC. It contains 2 input channels and outputs 12-bit conversion data.
Key Features
- Area: 0.09mm2 with IO and ESD
- Note: The area parameters are for reference only. Please refer to the final LEF file for the actual values.
- 12-bit resolution
- Up to 2MS/s sampling rate
- 4 single-ended input channels
- Current consumption: 2mA @ 2MS/s
- DNL< 2LSB, INL< 4LSB
Benefits
- Low power consumption
- Fully customizable
- Small area
- Simple integration process
Deliverables
- Databook and detailed physical implementation guides
- Complete set of timing models
- Library Exchange Format (LEF)
- Encrypted Verilog Models
- Layout vs. Schematic (LVS) report
- GDSII database
Technical Specifications
Foundry, Node
TSMC 55/28/6nm, HLMC 55nm, GF 55nm, UMC 55nm
GLOBALFOUNDRIES
In Production:
55nm
Silicon Proven: 55nm
Silicon Proven: 55nm
TSMC
In Production:
28nm
HPC
,
28nm
HPCP
,
28nm
HPM
,
55nm
LP
Silicon Proven: 6nm
Silicon Proven: 6nm
UMC
In Production:
55nm
Silicon Proven: 40nm
Silicon Proven: 40nm
Related IPs
- GP Successive Approximation A/D
- This analog-to-digital converter (ADC) uses successive approximation register (SAR) architecture to achieve 12-bit resolution.
- Successive Approximation ADC_2M10b
- Successive Approximation ADC_3M10b
- 12-Bit Low power successive-approximation ADC
- Low Power Successive-Approximation ADC 12.5 MS/s 12-Bit