Successive Approximation ADC_2M10b
Overview
Innosilicon SARADC IP is a small-sized, low power analog to digital converter with input channels. The converter is a charge-redistribution successive approximation ADC. It contains 16 input channels and outputs 10-bit conversion data.
Key Features
- Area: 0.425mm2 (850um x 500um) with IO and ESD
- Note: The area parameters are for reference only. Please refer to the final LEF file for the actual values.
- 10bit resolution
- Up to 2MS/s sampling rate
- 16 single-ended input channels
- Current consumption: 2mA @ 2MS/s
- DNL < 1LSB, INL < 2LSB
Benefits
- Low power consumption
- Fully customizable
- Small area
- Simple integration process
Deliverables
- Databook and detailed physical implementation guides
- Complete set of timing models
- Library Exchange Format (LEF)
- Encrypted Verilog Models
- Layout vs. Schematic (LVS) report
- GDSII database
Technical Specifications
Foundry, Node
SMIC 40nm, GF 40nm
GLOBALFOUNDRIES
In Production:
40nm
LP
Silicon Proven: 40nm LP
Silicon Proven: 40nm LP
SMIC
In Production:
40nm
LL
Silicon Proven: 40nm LL
Silicon Proven: 40nm LL
UMC
In Production:
40nm
Silicon Proven: 40nm
Silicon Proven: 40nm
Related IPs
- GP Successive Approximation A/D
- This analog-to-digital converter (ADC) uses successive approximation register (SAR) architecture to achieve 12-bit resolution.
- Successive Approximation ADC_2M12b
- Successive Approximation ADC_3M10b
- 12-Bit Low power successive-approximation ADC
- Low Power Successive-Approximation ADC 12.5 MS/s 12-Bit