The SPMI Verification IP provides an effective & efficient way to verify the SPMI master and slave components of an IP or SoC. The SPMI VIP is fully compliant with MIPI SPMI (1.0 and 2.0) Specifications, The VIP is lightweight with easy plug-and-play components so that there is no hit on the design cycle time.
SPMI Verification IP
Overview
Key Features
- Compliant with MIPI SPMI(1.0 and 2.0) specification.
- Supports multi-master and multi-slave model.
- Supports Bus Arbitration.
- Supports ACK/NACK mechanism.
- Supports Device Enumeration.
- Supports Master connect and disconnect protocol.
- Supports all optional commands.
- Supports Parity and Error handling mechanisms.
- Supports Callbacks for error injections
- Monitors detect and notify the testbench of significant events such as transactions, warnings, timing, and protocol violations.
- In-built coverage analysis
- SPMI VIP comes with a complete test suite to verify every feature
- SPMI VIP comes with a Transaction analyser and Performance Monitors.
Benefits
- Available in native System Verilog (UVM/OVM/ VMM) and Verilog
- Unique development methodology to ensure the highest levels of quality
- Availability of Compliance & Regression Test Suites
- 24X5 customer support
- Unique and customizable licensing models
- Exhaustive set of assertions and coverage points with connectivity examples for all the components
- Consistency of interface, installation, operation, and documentation across all our VIPs
- Provide complete solutions and easy integration in IP and SoC environment
Block Diagram
Deliverables
- SPMI Master/BFM/Agent
- SPMI Slave/BFM/Agent
- SPMI Monitor
- SPMI Scoreboard
- Testbench Configuration
- Test Suit (Available in Source code)
- Basic and Directed Protocol Tests
- Random Tests
- Error Scenario Tests
- Assertion & Cover Point Tests
- Integration Guide, User Manual and Release Notes