PCIe Gen 5 Verification IP

Overview

Key Features

• Support for 32.0 GT/s Data Rate per lane with backwards compatible.
• Optimizing the Link to skip equalization at lower Data Rates when supporting 32.0 GT/s(optional feature).
• Lower pin count in pipe interface when supporting 32.0 GT/s.
• Support for newly added phy serdes architecture in pipe specification 5.0 .
• Support for modified TS1 & TS2 order set.
• Compliant with PCI Express Specifications 4.0 v1.0 (16GT/s), 3.0 (8GT/s), 2.0 (5GT/s) and 1.1 (2.5GT/s).
• Verification IP configurable as PCI express Root Complex and Device Endpoint.
• Configurable LinkWidth: x1, x2, x4, x8, x12, x16, x32.
• Configurable original pipe width : 8,16,32,64 and for Serdes Architecture: 10, 20, 40, 80
• Supports Low Power management LTSSM states - L0s, L1, L2, L1 sub states,PCI- PM, ASPM.
• Advanced Error Reporting (AER) with optional Malformed TLP checks, ECRC and TLP Poisoning support.
• Compliance testing in TL, DLL & PL including power management test-suites.
• On the fly protocol checking using protocol check functions, static and dynamic assertion.
• Built in Coverage analysis.
• Provides a comprehensive user API (callbacks).
• Graphical ​analyser for all three Layers to show PCIe transactions for easy debugging.
• Complaint with Pipe specification 5.1
• Supports scale flow control and lane margining feature.
• Supports simplified replay timer and SR-IOV
• Supports 10-bit Tag as requester as well as completer.
• Support for ATS with latest ATS Specification revision 1.1.
• Supports LTR & FLR (Function Level Reset)

Block Diagram

Technical Specifications