MIPI D-PHY DSI TX (Transmitter) IP

Overview

The MXL-DPHY-DSI-TX is a high-frequency low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance Standard for D-PHY. The IP is configured as a MIPI master and consists of 4 lanes: 1 Clock lane and 3 data lanes, which makes it suitable for Display Interface Applications (DSI). The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed Data traffic while low power functions are mostly used for control.

Key Features

Consists of 1 Clock lane and 4 Data lanes
Complies with MIPI Standard 1.0 for D-PHY
Supports both high speed and low-power modes
80 Mbps to 1Gbps data rate in high speed mode
10 Mbps data rate in low-power mode
High Speed Serializer and Deserializer included
Low power dissipation
Include circuitry for production test

Benefits

Area and performance optimized for DSI TX.

Block Diagram

Applications

Mobile
Displays
IoT
VR/AR/MR
Consumer electronics
Automotive

Deliverables

Specifications
GDSII
LVS netlist
LEF file
IBIS Model
Verilog Model
Timing Model
Integration Guidelines
RTL
Documentation
One year support

Technical Specifications

Foundry, Node

Various, Upon request

Maturity

Silicon Proven

Availability

Now

TSMC

Silicon Proven: 65nm LP

Request Info