The Rambus Mem Test Analyzer Core from Rambus is used to capture the results from Rambus Memory Test Core.
The Mem Test Analyzer Core can be used in conjunction with the Memory Test Core to capture the actual and expected test data. The capture is initiated by an error trigger signal provided by the Memory Test Core. This data can then be retrieved from the Mem Test Analyzer Core via the chip’s configuration & status bus, on-chip processor or dedicated low-pin count serial port.
Rambus also offers easy-to-use scripts, driver and USBI2C bridge board to retrieve and analyze the data captured by the Data Analyzer Core.
The core is useful for chip and board validation. It provides low-cost, built-in logic analyzer capability similar in concept to the FPGA-based internal logic analyzer tools.
Mem Test Analyzer Core
Overview
Key Features
- Part of the Rambus comprehensive Memory Test Package
- Capture the results from the Rambus Memory Test Core
- Data retrieved via chip’s Configuration & Status bus, on-chip processor or dedicated low pin-count serial port
- Easy-to-use software including scripts and driver available
- Provides a low-cost, built-in logic analyzer capability
- Useful for chip and board validation
- Minimal ASIC gate count
- Broad range of ASIC and FPGA platforms supported
- Source code available
- Customization and Integration services available
Deliverables
- Core (Netlist or Source Code)
- Testbench (Source Code)
- Complete Documentation
- Expert Technical Support & Maintenance Updates
Technical Specifications
Foundry, Node
Any
Availability
Now