Innosilicon LVDS implements LVDS TIA/EIA protocol. Normally, Innosilicon LVDS contains four 7-bit parallel-load serial-out shift registers, a 7X clock PLL, and five Low-Voltage Differential Signaling (LVDS) line drivers in a single integrated circuit.
When transmitting, parallel data and pin_pdata_* are each loaded into registers upon the edge of the input clock signal (pin_pixel_clk). The frequency of pin_pixel_clk is multiplied seven times, and then used to unload the data registers in 7-bit slices and serially. The four serial streams and a phase-locked clock (CLKP/CLKN) are then output to LVDS output drivers. The frequency of CLKP/CLKN is the same as the input clock, pin_pixel_clk.
In addition, Innosilicon LVDS could extend from 5 lanes to N lanes (N is required by the customer). Therefore, the TTL lines extend respectively.
LVDS TX Combo TTL PHY
Overview
Key Features
- Compatible with ANSI TIA/EIA-644 LVDS and IEEE Std1596.3-1996 standards
- LVDS display SerDes interfaces directly to LCD display panels with integrated LVDS
- Supports byte clock mode
- Supports 7-bit parallel output per data lane in LVDS mode
- Supports data rate up to 1.5Gbps bandwidth per lane
- 200Mbps maximum data transfer rate per pad on TTL mode
- Parallel 7-bit pixel clock frequency ranging from 10MHz to 214MHz
- Embedded PLL supporting integer and fractional modes
- Supports built-in BIST test mode
- Supports 1 clock lane and extensible data lanes
Deliverables
- Databook and physical implementation guides Netlist (Spice format for LVS)
- Library Exchange Format (LEF)
- Verilog Models
- GDSII to Foundry IP Merge
- Module integration guidelines
- Silicon validation report (when available)
- Evaluation board (when available)
Technical Specifications
Foundry, Node
TSMC 12nm
TSMC
In Production:
12nm
Silicon Proven: 12nm , 40nm LP
Silicon Proven: 12nm , 40nm LP