INNOLINK-B Controller

Overview

The INNOLINK Controller (ILC) combined with INNOLINK PHY is a complete solution for high speed data communication between dies or chips. INNOLIN, GDDR like, single ended, up to 20Gbps/pin, typical MCM or short PCB application, bump pitch 80um~150um.
The ILC can support interface access through the standard AMBA4 AXI bus interfaces. The register interface is connected to the ILC through the standard AMBA 3.0 or 4.0 APB bus interfaces.
The Controller issues commands compliant with the DFI protocol through the DFI interface to the PHY module, which sends command/data to the other die and receives command/data from the other die.

Key Features

General Features
- Interrupt signals transmission supported
- Integrated adaptive flow control mechanism
- Built in ECC correct mechanism
- Error detect and packet retry supported
- Loopback test mode supported
- BIST logic integrated
- Similar with DFI 3.0 including: control, write/read data
- tx(rx)clk:ck_rate:data_rate = 1:2:16
DFI Features
- Supported
  - All typical control, write data and read data interface signals
- Unsupported
  - CtrlUpd interface
  - PhyMstr interface
  - Controller training mode
  - DFI disconnect protocol
- AXI Interface Features
  - Supported
    - Compatibility with the AMBA 4 AXI4 and AMBA 3 AXI protocols
    - Support for AXI burst types: fix, incremental and wrap
    - AXI clock asynchronous/synchronous to the controller clock
  - Unsupported
    - AXI QOS
    - Exclusive access support
  - APB Interface Features
    - Supported
      - APB 3P0
      - APB 4P0
    - Unsupported
      - APB 2P0

Benefits

Available in any 40nm or below technology nodes
Significantly lower cost, shorter time to market, lower supply risks for OEMs and simpler architectural partitioning than the monolithic silicon integration
Offers leading performance, power, and area per terabit
Flexible configuration with support for silicon interposer, package substrate and PCB options
Customizable synthesis for any FPGAs and ASICs
Full support from IP delivery to production

Applications

High performance computing (HPC) applications
Next-generation data center
Networking
5G communication
Artificial intelligence / machine learning (AI/ML) applications

Deliverables

Data book, Application notes
Verilog Getech File
SDC File
Simulation environment and user guide

Technical Specifications

Foundry, Node

TSMC, Samsung, SMIC, Global Foundies

Availability

now

SMIC

Pre-Silicon: 14nm

Samsung

Pre-Silicon: 14nm

TSMC

In Production: 12nm
Silicon Proven: 12nm

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