I3C

Overview

I3C (Improved Inter Integrated Circuit), which is enhanced with I2C protocol, and compatible with I2C. It adds new functions, including higher transmission speed, in-band interrupt, CRC check, and so on. Now, the I3C protocol is divided into MIPI and JEDEC. Usually, MIPI I3C is applied in sensor/IoT data transmission, and JEDEC I3C is applied in storage chip configuration.
Innosilicon I3C IP supports I3C master/slave functions, compliant with JESD403-1B and MIPI I3C. Users read and write the internal registers through the APB3.0 interface, and DMA is also supported for internal data buffer write or read. I3C Master converts the parallel data, which are configured by the users, into SDL/SDA serial data. At the same time, I3C Slave converts the data of register reading and writing into SCL/SDA.

Key Features

Supports two-wire serial interfaces: SDA/SCL
Supports primary master/slave only or dynamic configuration
Supports secondary master
Compliant with JESD403-1B and MIPI_I3C_Specification_V1.0
Supports independent data and command buffers and configurable in-depth
Supports working as the master device, providing a special buffer to obtain the device's characteristic information
Supports single command 65536 write/read bytes
Supports in-band interrupt with or without data
Backward compatible with I2C
Supports SCL frequencies up to 12.5MHz in I3C mode
Supports CRC/Parity check
Supports mixed fast bus for lower effective rate
Supports broadcast and directed CCC transfer
Supports private write and read
Supports interrupt interface which is used to report the interrupt to the software
DMA handshaking interface or internal DMA supports for data buffer
Supports APB3.0/4.0 for configuration and AHB/AXI interface for IP internal DMA
The configuration clock and core clock can be synchronous or asynchronous

Benefits

High speed
High efficiency
High reliability
Low power consumption

Applications

Mobile devices
IoT devices
Automotive electronics
Industrial automation
Medical device

Deliverables

Databook
Integration Guidelines
Soft driver design Guidelines
Frontend simulation environment and reports/Guidelines
If customers expect us to provide Backend and Layout service, the following additional deliverables will be included:
Encrypted IO spice netlist for SI evaluation
GDSII Layout and layer map for foundry merge
Place and Route LIB and LEF views for the AFE
LVS and DRC verification reports

Technical Specifications

Foundry, Node

Samsung 28nm, SMIC 40nm

SMIC

In Production: 40nm LL

Samsung

Pre-Silicon: 28nm FDS , 28nm LPP

Request Info

I3C