DP1.2 RX PHY

Overview

Innosilicon DP RX PHY is designed to receive and recover the video, audio and auxiliary data from a DP or eDP source device for display applications. It is composed of physical layer and PHY logic.
? The physical layer contains 4 data channels, an AUX channel and bias circuit.
? The 4 data channels serve as the main link to receive video and audio stream with a data rate up to 5.4Gbps. Each data channel consists of termination, equalizer and CDR circuit.
? The AUX channel employs half-duplex, bidirectional link to transmit and receive auxiliary information, such as EDID information and link status between a transmitter and a receiver device.
? The bias circuit generates voltage and current reference.
? The PHY logic receives the recovered parallel data and clocks signals of 4 data channels.
Innosilicon DP RX IP offers reliable implementation for DP or eDP interface, which can be integrated in the SOC used in multimedia device.

Key Features

Compliant with DP1.2 and eDP1.4 specifications
Supports 1/2/4-lane configuration
Up to 5.4Gbps per data lane
Typical 24MHz or 27MHz reference clock
Supports 20-bit parallel output up to 270MHz for each data channel
Supports AC-coupled input and termination connected to ground
Supports AUX channel working in 1MHz Manchester-II coding mode
Supports programmable termination, equalizer and CDR dynamics
Supports automatic termination resistance and offset calibration
Supports equalizer gain adaption
Supports BIST logic
APB3.0 slave interface for internal register access
Built-in bandgap reference

Benefits

Low power consumption
Fully customizable
Small area
Simple integration process
Available options include:

Test chips and test boards
FPGA integration support
Chip level integration

Deliverables

Datasheet
Physical Integration Guide
Timing Library Model (LIB)
Encrypted Verilog Model
Library Exchange Format (LEF)
GDSII Database
Evaluation Board if Available

Technical Specifications

Foundry, Node

SMIC 40nm

SMIC

In Production: 40nm LL
Silicon Proven: 40nm LL

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