MemConnect™ is a Comprehensive, Customizable, and Silicon Proven IP Solution for memory system design. It is a complete memory system supporting any combinations of SDR SDRAM, DDR, DDR2, Mobile SDR, FCRAM, Flash, EEPROM, SRAM and NAND Flash, all in one IP core. MemConnect supports a complete line of user interfaces including AMBA AHB, AXI, MIPS SysAD and EC interface, PowerPC, PCI, PCI-X, PCI Express, a built-in DMA controller, as well as a high performance simple user interfaces for shared memory access within an SOC design. Designers can customize and choose any combinations of memory type(s) and bus interface(s) for their applications without paying a penalty for unused logic. With flexibility and customization being an integral part of its design approach, MemConnect is ideally suitable for a wide range of applications, ranging from high-reliability memory systems for aerospace applications to high volume, low cost systems used in consumer applications.
How to start
MemConnect comes with the MemDesigner™ software which allows the user to customize the functions of the IP core according to his/her needs. With MemDesigner, the user has control over each individual block and has the ability to choose additional features such as arbitration or error correction (ECC). This allows the user to create a customized, complete subsystem, with the confidence that comes from quality and silicon proven IP.
Complete memory system supporting any combinations of SDR SDRAM, DDR, DDR2, Mobile SDR, FCRAM, Flash, EEPROM, SRAM and NAND Flash, all in one IP core
Overview
Key Features
- Comprehensive :
- Full range of memory choices: SDR SDRAM, DDR, DDR2, Mobile SDR, FCRAM, Flash, SRAM, EEPROM, NAND Flash.
- Full range of bus interfaces: AMBA AHB, MIPS SysAD and EC interface, PowerPC, PCI, PCI-X, PCI-Express and simple on-chip SOC interfaces.
- Customizable :
- Choice of memory type, frequency and combination of different memories.
- Configurable memory device organization, data width and depth.
- Configure the number of access ports to each memory.
- Ability to have different bus standard for each access port, with varying bus frequencies and data widths.
- Arbitration scheme for fair access or fixed priority access.
- Concurrent access from multiple ports when there is no resource conflict.
- Error correction code (ECC) for single-bit correction or customer specified ECC correction scheme.
- Data scrubbing and ECC error logging.
- Optional Direct Memory Access (DMA) controller.
- Supports :
- Supports ASIC and FPGA implementations.
- MemDesigner software allows the customer to configure their exact system.
- Verilog and VHDL RTL source code.
- Netlist and constraint files for specific FPGA targets.
- Comprehensive test benches.
- Single project or multiple use license, unlimited time and royalty free.
- One-year maintenance support.
Technical Specifications
Availability
now
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