The AMBA APB Verification IP provides an effective & efficient way to verify the components interfacing with the AMBA® APB bus of an IP or SoC. The AMBA APB VIP is fully compliant with standard AMBA® 2APB, AMBA® 3 APB v1.0, AMBA 3 APB v.2.0 (aka APB4), and AMBA APB5 specification from ARM. This VIP is a lightweight VIP with an easy plug-and-play interface so that there is no hit on the design cycle time.
AMBA APB 5,4,3,2 Verification IP
Overview
Key Features
- Compliant to AMBA APB5, AMBA APB v.2.0 (aka APB4), AMBA® 3 APB v1.0 and AMBA® 2APB.
- Support for all types of AMBA APB devices.
- Supports Parameterized data and address bus.
- Supports bus-endian converter/checker.
- Supports continuous transfer mode configuration (SETUPACCESS-SETUP) and protected accesses.
- Rich set of configuration parameters to control APB functionality including constrained randomization of protocol attributes.
- Supports various and Configurable types of memory accesses (read-only, secure, reserved etc.)
- Configurable wait states.
- Support for both secure and non-secure transactions.
- Support for Wakeup signals, User signals, and odd parity checking for all signals.
- Support for Realm Management Extension for physical address spaces.
- Supports UVM_RAL Model.
- Provides detailed performance monitoring for all the transfers.
- Supports advanced System Verilog features like constrained random testing.
- Supports dynamically configurable modes.
- Strong Protocol Monitor with real-time exhaustive programmable checks.
- Supports Dynamic as well as Static Error Injection scenarios.
- On-the-fly protocol checking using protocol check functions, static and dynamic assertion.
- Built-in Coverage analysis.
- Provides a comprehensive user API (callbacks) in all BFMs.
- Graphical analyzer to show transactions for easy debugging.
Block Diagram
Technical Specifications
Related IPs
- SPI Controller IP- Master/Slave, Parameterized FIFO, AMBA APB / AHB / AXI Bus
- SPI Controller IP- Master-only, Parameterized FIFO, AMBA APB / AHB / AXI Bus
- Enhanced SPI Controller IP- Master/Slave, Parameterized FIFO, AMBA APB / AHB / AXI Bus. Supports eSPI Master & Slave and SPI Master & Slave functions
- SPI Slave IP transfers to/from a AMBA APB, AXI, or AHB Interconnect
- AMBA APB 5,4,3,2 Verification IP
- I2C Controller IP – Master, Parameterized FIFO, APB Bus