IP Catalog > Analog IP > Clocking IP > PLL IP > General Purpose PLL IP > ADPLL 2GHz Clock Generator - GLOBALFOUNDRIES 22FDX

ADPLL 2GHz Clock Generator - GLOBALFOUNDRIES 22FDX

Overview

All-digital phase locked loop (ADPLL) clock generator for a nominal frequency of 2 GHz (0.8 V).

The Racyics® all-digital phase locked loop (ADPLL) clock generator is designed to generate a nominal 2 GHz multi-phase clock from a low-frequency reference with as little power and area overhead as possible. For highest flexibility, a wide range of reference frequencies for the Digitally Controlled Oscillator (DCO) is supported.

Key Features

  • Clock generation based on a Digitally Controlled Oscillator (DCO)
  • 800 MHz < = DCO frequency < = 2400 MHz
  • Programmable clock frequency dividers for ADPLL loop and clock outputs
  • lock-in < 25 us
  • 8-phase clock output (each 45° phase shift)
  • Compliant to automotive grade-1
  • allows reference frequency up to 150 MHz
  • < 15 ps RMS longterm jitter (measured over 1ms)
  • Characterization corners for - 40 °C to 150 °C

Block Diagram

ADPLL 2GHz Clock Generator - GLOBALFOUNDRIES 22FDX Block Diagram

Deliverables

  • Verilog simulation models
  • .lib / .db timing and power models (NLDM)
  • .lef layout abstract views
  • NDM and Milkyway libraries
  • GDSII layouts
  • LVS netlist

Technical Specifications

GLOBALFOUNDRIES
Pre-Silicon: 22nm FDX
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