180nm I/O Library with 1.5V to 3.3V GPIO
Overview
An I/O Library featuring three cells, a 1.5V to 3.3V GPIO, Power Pad for External VDD supply with ESD, and Ground Reference Pad with ESD. Includes Schmitt Trigger and 7.75V OTP tolerant.
Key Features
- Core Device: 1.6V
- I/O Device: 6V
- BEOL: 1P5M
- Pad: Wire bond, 110um inline pitch
- Cell height: 130um
- Temperature: -40C to 125C
- ESD: ±2kV HBM, ±500V CDM,
- Latch up: ±100mA @ +85C
Deliverables
- GDS
- Verilog and SCS simulation files
- Cadence Library Symbol, Spectre, and layouts
- CDL Netlist for DRC and LVS
- LEF's
- Full product ESD design review support for integration
- LIB Corner Files (10 included)
- IBIS
- IP Block diagram documentation
Technical Specifications
Foundry, Node
GlobalFoundries 180nm BCDLite
Maturity
Silicon-Proven
Availability
Immediate
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